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LMH6574_05 Datasheet, PDF (2/14 Pages) National Semiconductor (TI) – 4:1 High Speed Video Multiplexer | |||
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance
Human Body Model
Machine Model
Supply Voltage (V+ â Vâ)
IOUT (Note 3)
Signal & Logic Input Pin Voltage
Signal & Logic Input Pin Current
Maximum Junction Temperature
(Note 4)
2000V
200V
13.2V
130 mA
±(VS+0.6V)
±20 mA
+150ËC
Storage Temperature Range
Soldering Information
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
â65ËC to +150ËC
235 ËC
260 ËC
Operating Ratings (Note 1)
Operating Temperature
Supply Voltage Range
Thermal Resistance
Package
14-Pin SOIC
â40 ËC to 85 ËC
6V to 12V
(θJA)
130ËC/W
(θJC)
40ËC/W
±5V Electrical Characteristics
VS = ±5V, RL = 100â¦, AV = 2 V/V, RF = 575 â¦, TJ = 25 ËC, Unless otherwise specified. Bold numbers specify limits at tem-
perature extremes.
Symbol
Parameter
Conditions (Note 2)
Min
Typ
Max
Units
Frequency Domain Performance
SSBW
LSBW
.1 dBBW
DG
DP
XTLK
â3 dB Bandwidth
â3 dB Bandwidth
0. 1 dB Bandwidth
Differential Gain
Differential Phase
Channel to Channel Crosstalk
VOUT = 0.5 VPP
VOUT = 2 VPP
VOUT = 0.25 VPP
RL = 150â¦, f = 4.43 MHz
RL = 150â¦, f = 4.43MHz
All Hostile, 5 MHz
500
MHz
400
MHz
150
MHz
0.02
%
0.05
deg
â85
dB
Time Domain Response
TRS
Channel to Channel Switching Time Logic Transition to 90% Output
8
ns
Enable and Disable Times
Logic Transition to 90% or 10%
10
ns
Output
TRL
Rise and Fall Time
4V Step
2.4
ns
TSS
Settling Time to 0.05%
2V Step
17
ns
OS
Overshoot
2V Step
5
%
SR
Slew Rate
4V Step
2200
V/µs
Distortion
HD2
2nd Harmonic Distortion
HD3
3rd Harmonic Distortion
IMD
3rd Order Intermodulation Products
2 VPP , 5 MHz
2 VPP , 5 MHz
10 MHz, Two Tones 2 VPP at
Output
â68
dBc
â84
dBc
â80
dBc
Equivalent Input Noise
VN
Voltage
ICN
Current
>1 MHz, Input Referred
>1 MHz, Input Referred
5
nV
5
pA/
Static, DC Performance
CHGM Channel to Channel Gain
Difference
VIO
Input Offset Voltage (Note 5)
DC, Difference in Gain Between
Channels
VIN = 0V
±0.005 ±0.032
±0.035
%
1
±20
±25
mV
DVIO
IBN
Offset Voltage Drift
Input Bias Current (Notes 7, 5)
VIN = 0V
30
µV/ËC
â3
±5
±5.6
µA
DIBN
Bias Current Drift
Inverting Input Bias Current
PSRR
Power Supply Rejection Ratio
(Note 5)
Pin 12, Feedback Point,
VIN = 0V
DC, Input Referred
11
nA/ËC
â7
±10
±13
47
54
dB
45
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