LMH6574_05 Datasheet, PDF (13/14 Pages) National Semiconductor (TI) – 4:1 High Speed Video Multiplexer

Other Applications (Continued)
20119714
FIGURE 8. Frequency Response vs. Capacitive Load
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation
board as a guide. The LMH730276 is the evaluation board
supplied with samples of the LMH6574. To reduce parasitic
capacitances, ground and power planes should be removed
near the input and output pins. For long signal paths con-
trolled impedance lines should be used, along with imped-
ance matching elements at both ends. Bypass capacitors
should be placed as close to the device as possible. Bypass
capacitors from each rail to ground are applied in pairs. The
larger electrolytic bypass capacitors can be located farther
from the device, the smaller ceramic capacitors should be
placed as close to the device as possible. In Figure 1, the
capacitor between V⁺ and V^− is optional, but is recom-
mended for best second harmonic distortion. Another way to
enhance performance is to use pairs of 0.01 µF and 0.1 µF
ceramic capacitors for each supply bypass.
POWER DISSIPATION
The LMH6574 is optimized for maximum speed and perfor-
mance in the small form factor of the standard SOIC pack-
age. To ensure maximum output drive and highest perfor-
mance, thermal shutdown is not provided. Therefore, it is of
utmost importance to make sure that the T_JMAX is never
exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissi-
pation for the LMH6574:
1. Calculate the quiescent (no-load) power: P_AMP = I_CC*
(V_S), where V_S = V⁺ - V^−.
2. Calculate the RMS power dissipated in the output stage:
P_D (rms) = rms ((V_S - V_OUT) * I_OUT), where V_OUT and
I_OUT are the voltage across and the current through the
external load and V_S is the total supply voltage.
3. Calculate the total RMS power: P_T = P_AMP + P_D.
The maximum power that the LMH6574 package can dissi-
pate at a given temperature can be derived with the following
equation:
P_MAX = (150˚ – T_AMB)/ θ_JA, where T_AMB = Ambient tempera-
ture (˚C) and θ_JA = Thermal resistance, from junction to
ambient, for a given package (˚C/W). For the SOIC package
θ_JA is 130 ˚C/W.
ESD PROTECTION
The LMH6574 is protected against electrostatic discharge
(ESD) on all pins. The LMH6574 will survive 2000V Human
Body model and 200V Machine model events. Under normal
operation the ESD diodes have no effect on circuit perfor-
mance. There are occasions, however, when the ESD di-
odes will be evident. If the LMH6574 is driven by a large
signal while the device is powered down the ESD diodes will
conduct . The current that flows through the ESD diodes will
either exit the chip through the supply pins or will flow
through the device, hence it is possible to power up a chip
with a large signal applied to the input pins. Using the
shutdown mode is one way to conserve power and still
prevent unexpected operation.
EVALUATION BOARDS
National Semiconductor provides the following evaluation
boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the data sheet
plots were measured with this board.
Device
LMH6574
Package
SOIC
Evaluation Board
LMH730276
An evaluation board can be shipped when a sample request
is placed with National Semiconductor. Samples can be
ordered on the National web page. (www.national.com)
13
www.national.com