LB-9 Datasheet, PDF (2/3 Pages) National Semiconductor (TI) – Universal Balancing Techniques

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FIGURE 3. Offset Voltage Adjustment for
Non-Inverting Amplifiers
A voltage follower may be balanced by the technique shown
in Figure 4. R₁ injects a current which produces a voltage
drop across R₃ to cancel the offset voltage. The addition of
the adjustment resistors causes a gain error, increasing the
gain by 0.05%. This small error usually causes no problem.
The adjustment circuit essentially causes the offset voltage
to appear at full output, rather than at low output levels,
where it is a large percentage error.
FIGURE 4. Offset Voltage Adjustment for
Voltage Followers
Differential amplifiers are somewhat more difficult to bal-
ance. The offset adjustment used for a differential amplifier
can degrade the common mode rejection ratio. Figure 5
shows an adjustment circuit which has minimal effect on the
common mode rejection. The voltage at the arm of the pot is
divided by R₄ and R₅ to supply an offset correction of ±7.5
mV. R₄ and R₅ are chosen such that the common mode
rejection ratio is limited by the amplifer for values of R₃
greater than 1 kΩ. If R₃ is less than 1k the shunting of R₄ by
R₅ must be considered when choosing the value of R₃.
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FIGURE 5. Offset Voltage Adjustment for
Differential Amplifiers
The techniques described for balancing offset voltage at the
input of the amplifier offer two main advantages: First, they
are universally applicable to all operational amplifiers and
allow device interchangeability with no modifications to the
balance circuitry. Second, they permit balancing without in-
terfering with the internal circuitry of the amplifier. The elec-
trical parameters of the amplifiers are tested and guaranteed
without balancing. Although it doesn’t usually happen, bal-
ancing could degrade performance.
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