LB-9 Datasheet, PDF (1/3 Pages) National Semiconductor (TI) – Universal Balancing Techniques

Universal Balancing
Techniques
National Semiconductor
Linear Brief 9
August 1969
IC op amps are widely accepted as a universal analog
component. Although the circuit designs may vary, most
devices are functionally interchangeable. However, offset
voltage balancing remains a personality trait of the particular
amplifier design. The techniques shown here allow offset
voltage balancing without regard to the internal circuitry of
the amplifier.
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R1 = 2000 R3 \ R4
R4 \ R3 ≤ 10 kΩ
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FIGURE 1. Offset Voltage Adjustment for Inverting
Amplifiers Using 10 kΩ Source Resistance or Less
The circuit shown in Figure 1 is used to balance out the
offset voltage of inverting amplifiers having a source resis-
tance of 10 kΩ or less. A small current is injected into the
summing node of the amplifier through R₁. Since R₁ is 2000
times as large as the source resistance the voltage at the
arm of the pot is attenuated by a factor of 2000 at the
summing node. With the values given and ±15V supplies the
output may be zeroed for offset voltages up to ±7.5 mW.
If the value of the source resistance is much larger than 10
kΩ, the resistance needed for R₁ becomes too large. In this
case it is much easier to balance out the offset by supplying
a small voltage at the non-inverting input of the amplifier.
Figure 2 shows such a scheme. Resistors R₁ and R₂ divide
the voltage at the arm of the pot to supply a ±7.5 mW
adjustment range with ±15V supplies.
This adjustment method is also useful when the feedback
element is a capacitor or non-linear device.
FIGURE 2. Offset Voltage Adjustment for Inverting
Amplifiers Using Any Type of Feedback Element
This technique of supplying a small voltage effectively in
series with the input is also used for adjusting non-inverting
amplifiers. As is shown in Figure 3, divider R₁, R₂ reduces
the voltage at the arm of the pot to ±7.5 mW for offset
adjustment. Since R₂ appears in series with R₄, R₂ should
be considered when calculating the gain. If R₄ is greater than
10 kΩ the error due to R₂ is less than 1%.
© 2002 National Semiconductor Corporation AN008460
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