DS90UR241_10 Datasheet, PDF (2/4 Pages) National Semiconductor (TI) – Spread Spectrum Tolerance Support Three key parameters, frequency

1
0
-1
-2
-3
-4
-5
0.01
0.1
1
10
INPUT JITTER FREQUENCY (MHz)
30126402
FIGURE 2. Example of PLL Jitter Transfer (Theoretical)
When viewing the frequency spectra, the energy should be
spread evenly across a range as defined by the frequency
deviation. Outside of the specified range, the energy should
quickly reduce to baseline levels. Additional “peaks” outside
the desired deviation range are undesirable, resulting in a
high frequency component which the PLL will not track.
Theory of Operation: Serializer and
Deserializer PLL Response to Jitter
The bandwidth of the device PLL determines its fundamental
response to jitter. Input jitter with a frequency below the band-
width of the PLL – “low frequency jitter” – will be tracked and
passed to the output of the PLL. As frequencies increase
above the PLL bandwidth, “high frequency” jitter begins to be
attenuated as per the jitter transfer curve. Maximum attenu-
ation is achieved beyond the −6dB point. A typical PLL jitter
transfer curve is shown in Figure 2. This illustrates gain (ratio
of PLL input to output jitter) vs. the frequency of the jitter.
At the serializer input, jitter frequencies below the serializer
bandwidth will be tracked by the PLL, and passed along the
serial link to the downstream deserializer. Jitter with a fre-
quency above the serializer bandwidth will be attenuated to
some degree as defined by the PLL’s jitter transfer curve.
Now let’s consider the input to the deserializer. As with the
serializer, any jitter below the deserializer bandwidth will be
tracked by the PLL and pass to the deserializer’s outputs.
Frequencies above the deserializer bandwidth are not
tracked, and must be considered with respect to the receiver’s
input jitter tolerance specification. For the DS90UR241/124 to
operate properly, the deserializer's input jitter tolerance spec-
ification (RxINTOL) must be satisfied. High frequency jitter -
at frequencies >2MHz - will not be tracked and must remain
below 0.5UI.
The purpose of the serializer's input jitter specification is to
ensure that jitter contributed by the serializer output is limited
such that deserializer's RxINTOL may be satisfied by the sys-
tem. When a typical SSC modulation profile is applied (tri-
ange, Lexmark profile) the behavior of the serializer PLL is
predictable and follows the PLL jitter transfer curve. At fre-
quencies above the serializer bandwidth (2.6MHz), the input
jitter will be attenuated. Therefore, it is critical to limit the jitter
at frequencies in the range of 2 - 2.6MHz. This is the range in
which the serializer maximum input jitter specification of
0.25UI must be applied. At input jitter frequencies above
2.6MHz, the magnitude of jitter should remain below 0.4UI.
Serializer Input Jitter across TCLK
Frequency
TCLK Frequency Jitter Frequency Maximum
(MHz)
(MHz)
Jitter pk-pk
(ps)
43
2 - 2.6
200
> 2.6
300
33
2 - 2.6
260
> 2.6
400
25
2 - 2.6
340
> 2.6
550
Alternate Modulation Profiles
The supported modulation profiles, triangle and Lexmark,
modulate the clock at a single frequency and do not generate
abrupt frequency steps. Some alternative SSC modulation
profiles have been shown to exhibit abrupt frequency steps,
and thus are not recommended. The instantaneous frequen-
cy step results in a frequency error, appearing as excessive
jitter at the output of the serializer PLL. Under these conditions
the serializer input jitter specification cannot be used to pre-
dict the behavior of the serializer output and guarantee link
performance. If an alternate modulation profile is employed,
the user must guarantee system operation by measuring the
jitter at the receiver input to ensure the RxINTOL specification
is satisfied
Response to SSC source
Spread spectrum clock sources modulate at frequencies well
below the bandwidth of the PLLs. This low frequency modu-
lation is easily tracked by the PLLs, and passes along cleanly
to the output of the deserializer. However, the generated SSC
signal will have additional frequency components, some of
which may appear as high frequency jitter or frequency dis-
continuities. Depending upon the frequency and magnitude
of these additional jitter components, input jitter tolerance
www.national.com
2