DS90UR241_10 Datasheet, PDF (1/4 Pages) National Semiconductor (TI) – Spread Spectrum Tolerance Support Three key parameters, frequency

DS90UR241/124 Spread
Spectrum Tolerance
Support
National Semiconductor
Application Note 2068
December 2, 2010
Compliance to EMI limits is often a challenge. Spread spec-
trum clocking is commonly used to minimize EMI. The effect
of modulating periodic signals, both clock and data, reduces
the peak emissions by spreading the energy over a range of
frequencies. The DS90UR241 and DS90UR124 chipset al-
lows the use of spread spectrum clock and data inputs. The
following is a discussion of spread spectrum clock character-
istics and the interaction with DS90UR241/124 chipset.
Spread Spectrum Modulation
Three key parameters, frequency deviation, modulation fre-
quency and modulation profile, are used to define a spread
spectrum output. Most spread spectrum generators will mod-
ulate the fundamental clock frequency by several percent.
This modulation may be “center spread” or “down spread”.
The rate of this frequency change, modulation frequency, is
often quite slow in comparison to the fundamental clock fre-
quency - typically in the 10’s of kHz range.
Table 1 provides guidance for the frequency deviation and
modulation frequencies supported by the DS90UR241/124
chipset. This data is based on testing with an ideal source.
The input clock signal was modulated by the triangle output
of an arbitrary waveform generator. There was a direct con-
nection between serializer and deserializer (no cable). No
effects of additional jitter or cable length are included.
Additional factors associated with spread spectrum operation
must also be considered. A modulated clock output may con-
tain additional higher frequency jitter components – beyond
the modulation frequency. It is important that this additional
jitter not exceed the input jitter tolerance of the downstream
device. Per the DS90UR241 specification, the input jitter tol-
erance is ±100ps (200ps pk-pk) at the maximum operating
frequency of 43MHz. This value scales with input clock peri-
od. For example, at 33MHz the recommended input clock
jitter maximum increases to 260ps pk-pk. Please refer to the
Appendix for a description of measuring peak-to-peak jitter.
The frequency profile of the modulated signal is also impor-
tant. There are two common modulation profiles – triangle and
Lexmark (“Hershey Kiss”). Both apply a fixed modulation rate
to the clock signal, and are proven to effectively reduce EMI.
The DS90UR241/124 is targeted to support these two pro-
files. Note that some other profiles do exist, with slightly
different behavior (i.e. varying the modulation rate over a
range of frequencies). The DS90UR241/124 is not guaran-
teed to operate properly with these alternative modulation
profiles.
FIGURE 1. SSC Triangle Modulation
30126401
TABLE 1. Frequency and Modulation Frequencies for SSC (Triangle Modulation Profile)
Maximum f_dev
±4% center spread (8% total)
±2% center spread (4% total)
Maximum f_mod
PCLK = 33 MHz
PCLK = 8 MHz
20 kHz
5 kHz
50 kHz
25 kHz
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