DS64EV100_08 Datasheet, PDF (2/10 Pages) National Semiconductor (TI) – Programmable Single Equalizer

Pin Diagram
20196402
14-Pin LLP Package (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch)
See NS Package Number SQA14A
Ordering Information
NSID
DS64EV100SD
DS64EV100SDX
Package Type, Qty Size
14–pin LLP (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch, reel of 1000
14–pin LLP (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch, reel of 4500
Package ID
SDA14A
SDA14A
Pin Descriptions
Pin Name
Pin #
I/O,
Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN+
3
I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating
IN−
4
resistor is connected between IN+ and IN-. Refer to Figure 4.
OUT+
12
O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
OUT−
11
terminating resistor connects OUT+ to V_DD and OUT- to V_DD.
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
14
I, CMOS BST_2, BST_1, and BST_0 select the equalizer strength. BST_2 is internally pulled high. BST_1
7
and BST_0 are internally pulled low.
8
POWER
V_DD
GND
5
2, 6, 9, 10,
13
I, Power V_DD = 2.5V ±5% or 3.3V ±10%. V_DD pins should be tied to V_DD plane through low inductance
path. A 0.01μF bypass capacitor should be connected between each V_DD pin to GND planes.
I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance path.
DAP
PAD
I, Power Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board.
OTHER
NC
1
Reserved. Do not connect.
Note: I = Input, O = Output
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