74HC160 Datasheet, PDF (2/6 Pages) NXP Semiconductors – Presettable synchronous BCD decade counter; asynchronous reset

Absolute Maximum Ratings (Notes 1 2)
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Supply Voltage (V_CC)
DC Input Voltage (V_IN)
DC Output Voltage (V_OUT)
Clamp Diode Current (I_IK I_OK)
DC Output Current per pin (I_OUT)
DC V_CC or GND Current per pin (I_CC)
Storage Temperature Range (T_STG)
Power Dissipation (P_D)
(Note 3)
S O Package only
b0 5 to a7 0V
b1 5 to V_CCa1 5V
b0 5 to V_CCa0 5V
g20 mA
g25 mA
g50 mA
b65 C to a150 C
600 mW
500 mW
Lead Temp (T_L) (Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage (V_CC)
DC Input or Output Voltage
(V_IN V_OUT)
Operating Temp Range (T_A)
MM74HC
MM54HC
Min
2
0
b40
b55
Input Rise or Fall Times
(t_r t_f)
V_CCe2 0V
V_CCe4 5V
V_CCe6 0V
Max
6
V_CC
a85
a125
1000
500
400
Units
V
V
C
C
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
V_CC
T_Ae25 C
Typ
74HC
54HC
T_Aeb40 to 85 C T_Aeb55 to 125 C
Guaranteed Limits
Units
V_IH
Minimum High Level
Input Voltage
2 0V
4 5V
6 0V
15
15
3 15
3 15
42
42
15
V
3 15
V
42
V
V_IL
Maximum Low Level
Input Voltage
2 0V
4 5V
6 0V
05
05
1 35
1 35
18
18
05
V
1 35
V
18
V
V_OH
Minimum High Level V_INeV_IH or V_IL
Output Voltage
l^IOUTl^{s20 mA}
2 0V 2 0 1 9
19
4 5V 4 5 4 4
44
6 0V 6 0 5 9
59
19
V
44
V
59
V
V_INeV_IH or V_IL
l^IOUTl^{s4 0 mA}
4 5V 4 2 3 98
3 84
l^IOUTl^{s5 2 mA}
6 0V 5 7 5 48
5 34
V_OL
Maximum Low Level V_INeV_IH or V_IL
Output Voltage
l^IOUTl^{s20 mA}
2 0V 0 0 1
01
4 5V 0 0 1
01
6 0V 0 0 1
01
37
V
52
V
01
V
01
V
01
V
V_INeV_IH or V_IL
l^IOUTl^{s4 0 mA}
l^IOUTl^{s5 2 mA}
4 5V 0 2 0 26
6 0V 0 2 0 26
I_IN
Maximum Input
V_INeV_CC or GND 6 0V
Current
g0 1
0 33
0 33
g1 0
04
V
04
V
g1 0
mA
I_CC
Maximum Quiescent V_INeV_CC or GND 6 0V
80
80
Supply Current
I_OUTe0 mA
160
mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (V_OH and V_OL) occur for HC at 4 5V Thus the 4 5V values should be used when designing
with this supply Worst case V_IH and V_IL occur at V_CCe5 5V and 4 5V respectively (The V_IH value at 5 5V is 3 85V ) The worst case leakage current (I_IN I_CC and
I_OZ) occur for CMOS at the higher voltage and so the 6 0V values should be used
V_IL limits are currently tested at 20% of V_CC The above V_IL specification (30% of V_CC) will be implemented no later than Q1 CY’89
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