74HC160 Datasheet, PDF (1/6 Pages) NXP Semiconductors – Presettable synchronous BCD decade counter; asynchronous reset

January 1992
MM74HC160 Synchronous
Decade Counter with Asynchronous Clear
MM54HC161 MM74HC161 Synchronous
Binary Counter with Asynchronous Clear
MM54HC162 MM74HC162 Synchronous
Decade Counter with Synchronous Clear
MM54HC163 MM74HC163 Synchronous
Binary Counter with Synchronous Clear
General Description
The MM54HC160 MM74HC160 MM54HC161
MM74HC161 MM54HC162 MM74HC162 and
MM54HC163 MM74HC163 synchronous presettable count-
ers utilize advanced silicon-gate CMOS technology and in-
ternal look-ahead carry logic for use in high speed counting
applications They offer the high noise immunity and low
power consumption inherent to CMOS with speeds similar
to low power Schottky TTL The ’HC160 and the ’HC162 are
4 bit decade counters and the ’HC161 and the ’HC163 are
4 bit binary counters All flip-flops are clocked simultaneous-
ly on the low to high transition (positive edge) of the CLOCK
input waveform
These counters may be preset using the LOAD input Pre-
setting of all four flip-flops is synchronous to the rising edge
of CLOCK When LOAD is held low counting is disabled and
the data on the A B C and D inputs is loaded into the
counter on the rising edge of CLOCK If the load input is
taken high before the positive edge of CLOCK the count
operation will be unaffected
All of these counters may be cleared by utilizing the CLEAR
input The clear function on the MM54HC162 MM74HC162
and MM54HC163 MM74HC163 counters are synchronous
to the clock That is the counters are cleared on the posi-
tive edge of CLOCK while the clear input is held low
The MM54HC160 MM74HC160 and MM54HC161
MM74HC161 counters are cleared asynchronously When
the CLEAR is taken low the counter is cleared immediately
regardless of the CLOCK
Two active high enable inputs (ENP and ENT) and a RIP-
PLE CARRY (RC) output are provided to enable easy cas-
cading of counters Both ENABLE inputs must be high to
count The ENT input also enables the RC output When
enabled the RC outputs a positive pulse when the counter
overflows This pulse is approximately equal in duration to
the high level portion of the Q_A output The RC output is fed
to successive cascaded stages to facilitate easy implemen-
tation of N-bit counters
All inputs are protected from damage due to static dis-
charge by diodes to V_CC and ground
Features
Y _{Typical operating frequency 40 MHz}
Y _{Typical propagation delay clock to Q 18 ns}
Y _{Low quiescent current 80 mA maximum (74HC Series)}
Y _{Low input current 1 mA maximum}
Y _{Wide power supply range 2 – 6V}
Connection Diagram
TL F 5008 – 1
Order Number MM54HC161 162 163
or MM74HC160 161 162 163
Truth Tables
’HC160 HC161
CLK CLR ENP ENT Load
Function
X
L
XX
X
Clear
XHHL
H Count RC disabled
X
H
L
H
H
Count disabled
XH
L
L
H Count RC disabled
uH X X L
Load
uH
H
H
H
Increment Counter
H e high level L e low level
u X e don’t care e low to high transition
’HC162 HC163
CLK CLR ENP ENT Load
Function
uL X X X
Clear
XHHL
H Count RC disabled
X
H
L
H
H
Count disabled
XH
L
L
H Count RC disabled
uH X X L
Load
uH
H
H
H
Increment Counter
C1995 National Semiconductor Corporation TL F 5008
RRD-B30M115 Printed in U S A