54F379DM Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – Quad Parallel Register with Enable

Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
Input I_IH I_IL
HIGH LOW Output I_OH I_OL
E
D₀ – D₃
CP
Q₀ – Q₃
Q₀ – Q₃
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
Complement Outputs
10 10
10 10
10 10
50 33 3
50 33 3
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
The ’F379 consists of four edge-triggered D-Type flip-flops
with individual D inputs and Q and Q outputs The Clock
(CP) and Enable (E) inputs are common to all flip-flops
When the E is input HIGH the register will retain the present
data independent of the CP input The D_n and E inputs can
change when the clock is in either state provided that the
recommended setup and hold times are observed
Truth Table
Inputs
E
CP
D_n
H
L
X
L
L
H
L
L
L
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Transition
NC e No Change
Logic Diagram
Outputs
Q_n
Q_n
NC
NC
H
L
L
H
TL F 9527 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2