54F379DM Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Quad Parallel Register with Enable

August 1995
54F 74F379
Quad Parallel Register with Enable
General Description
The ’F379 is a 4-bit register with buffered common Enable
This device is similar to the ’F175 but features the common
Enable rather than common Master Reset
Features
Y _{Edge triggered D-type inputs}
Y _{Buffered positive edge-triggered clock}
Y _{Buffered common enable input}
Y _{True and complement outputs}
Y _{Guaranteed 4000V minimum ESD protection}
Commercial
74F379PC
74F379SC (Note 1)
74F379SJ (Note 1)
Military
54F379DM (QB)
54F379FM (QB)
54F379LM (QB)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 300 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Logic Symbols
Connection Diagrams
IEEE IEC
Pin Assignment
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9527–5
TL F 9527 – 1
TL F 9527 – 2
TL F 9527–3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9527
RRD-B30M115 Printed in U S A