54F280DM Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – 9-Bit Parity Generator/Checker

Unit Loading Fan Out
Pin Names
Description
I₀ – I₈
R_O
R_E
Data Inputs
Odd Parity Output
Even Parity Output
54F 74F
UL
HIGH LOW
10 10
50 33 3
50 33 3
Input I_IH I_IL
Output I_OH I_OL
20 mA b0 6 mA
b1 mA 20 mA
b1 mA 20 mA
Truth Table
Logic Diagram
Number of
HIGH Inputs
I₀ – I₈
02468
13579
H e HIGH Voltage Level
L e LOW Voltage Level
Outputs
R Even
R Odd
H
L
L
H
TL F 9512 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2