54F280DM Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – 9-Bit Parity Generator/Checker

August 1995
54F 74F280
9-Bit Parity Generator Checker
General Description
The ’F280 is a high-speed parity generator checker that ac-
cepts nine bits of input data and detects whether an even or
an odd number of these inputs is HIGH If an even number
of inputs is HIGH the Sum Even output is HIGH If an odd
number is HIGH the Sum Even output is LOW The Sum
Odd output is the complement of the Sum Even output
Features
Y _{Guaranteed 4000V minimum ESD protection}
Commercial
74F280PC
74F280SC (Note 1)
74F280SJ (Note 1)
Military
54F280DM (Note 2)
54F280FM (Note 2)
54F280LM (Note 2)
Package
Number
N14A
J14A
M14A
M14D
W14B
E20A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9512–3
IEEE IEC
TL F 9512 – 1
TL F 9512 – 2
TL F 9512–5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9512
RRD-B30M115 Printed in U S A