100331 Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – Low Power Triple D Flip-Flop

Logic Diagram
Truth Tables
Synchronous Operation
(Each Flip-Flop)
Inputs
D_n
CP_n
CP_C
MS
MR
SD_n
CD_n
L
N
L
L
L
H
N
L
L
L
L
L
N
L
L
H
L
N
L
L
X
L
L
L
L
X
H
X
L
L
X
X
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
U = Undefined
t = Time before CP Positive Transition
t + 1 = Time after CP Positive Transition
N = LOW to HIGH Transition
Outputs
Q_n(t + 1)
L
H
L
H
Qn(t)
Qn(t)
Qn(t)
DS100300-5
Asynchronous Operation
(Each Flip-Flop)
Inputs
D_n
CP_n
CP_C
MS
MR
SD_n
CD_n
X
X
X
H
L
X
X
X
L
H
X
X
X
H
H
Outputs
Q_n(t + 1)
H
L
U
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