100331 Datasheet, PDF (1/8 Pages) National Semiconductor (TI) – Low Power Triple D Flip-Flop

August 1998
100331
Low Power Triple D Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP_C), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP_n), Direct
Set (SD_n) and Direct Clear (CD_n) inputs. Data enters a mas-
ter when both CP_n and CP_C are LOW and transfers to a
slave when CP_n or CP_C (or both) go HIGH. The Master Set,
Master Reset and individual CD_n and SD_n inputs override
the Clock inputs. All inputs have 50 kΩ pull-down resistors.
Features
n 35% power reduction of the 100131
n 2000V ESD protection
n Pin/function compatible with 100131
n Voltage compensated operating range = −4.2V to −5.7V
n Available to industrial grade temperature range
n Available to Standard Microcircuit Drawing (SMD)
5962-9153601
Logic Symbol
Pin Names
CP₀–CP₂
CP_C
D₀– D₂
CD₀–CD₂
SD_n
MR
MS
Q₀-Q₂
Q₀– Q₂
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
DS100300-1
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100300-2
DS100300-3
© 1998 National Semiconductor Corporation DS100300
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