LP3958 Datasheet, PDF (19/28 Pages) National Semiconductor (TI) – Lighting Management Unit with High Voltage Boost Converter

I²C Compatible Interface
I²C SIGNALS
The SCL pin is used for the I²C clock and the SDA pin is
used for bidirectional data transfer. Both these signals need
a pull-up resistor according to I²C specification.
I²C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
I²C Signals: Data Validity
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I²C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I²C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I²C master always
generates START and STOP bits. The I²C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I²C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9^th clock pulse, signifying an acknowl-
edge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I²C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3958
address is 59H (101 1001b). For the eighth bit, a “0” indi-
cates a WRITE and a “1” indicates a READ. This means that
the first byte is B2H for WRITE and B3H for READ. The
second byte selects the register to which the data will be
written. The third byte contains data to write to the selected
register.
I²C Chip Address
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Register changes take an effect at the SCL rising edge
during the last ACK from slave.
I²C Start and Stop Conditions
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