LM3424 Datasheet, PDF (18/50 Pages) National Semiconductor (TI) – Constant Current N-Channel Controller with Thermal Foldback for Driving LEDs

PWM DIMMING
The active low nDIM pin can be driven with a PWM signal
which controls the main NFET and the dimming FET (dim-
FET). The brightness of the LEDs can be varied by modulat-
ing the duty cycle of this signal. LED brightness is approxi-
mately proportional to the PWM signal duty cycle, (i.e. 30%
duty cycle ~ 30% LED brightness). This function can be ig-
nored if PWM dimming is not required by using nDIM solely
as a V_IN UVLO input as described in the Input Under-Voltage
Lockout section or by tying it directly to V_CC or V_IN.
tance helps source current into the load, improving the LED
current rise time.
A minimum on-time must be maintained in order for PWM
dimming to operate in the linear region of its transfer function.
Because the controller is disabled during dimming, the PWM
pulse must be long enough such that the energy intercepted
from the input is greater than or equal to the energy being put
into the LEDs. For boost and buck-boost regulators, the min-
imum dimming pulse length in seconds (t_PULSE) is:
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FIGURE 16. PWM Dimming Circuit
Figure 16 shows how the PWM signal is applied to nDIM:
1. Connect the dimming MosFET (Q_DIM) with the drain to
the nDIM pin and the source to GND. Apply an external
logic-level PWM signal to the gate of Q_DIM.
2. Connect the anode of a Schottky diode (D_DIM) to the
nDIM pin. Apply an inverted external logic-level PWM
signal to the cathode of the same diode.
The DDRV pin is a PWM output that follows the nDIM PWM
input signal. When the nDIM pin rises, the DDRV pin rises and
the PWM latch reset signal is removed allowing the main
MosFET Q1 to turn on at the beginning of the next clock set
pulse. In boost and buck-boost topologies, the DDRV pin is
used to control a N-channel MosFET placed in series with the
LED load, while it would control a P-channel MosFET in par-
allel with the load for a buck topology.
The series dimFET will open the LED load, when nDIM is low,
effectively speeding up the rise and fall times of the LED cur-
rent. Without any dimFET, the rise and fall times are limited
by the inductor slew rate and dimming frequencies above
1 kHz are impractical. Using the series dimFET, dimming fre-
quencies up to 30 kHz are achievable. With a parallel dimFET
(buck topology), even higher dimming frequencies are
achievable.
When using the PWM functionality in a boost regulator, the
PWM signal drives a ground referenced FET. However, with
buck-boost and buck topologies, level shifting circuitry is nec-
essary to translate the PWM dim signal to the floating dimFET
as shown in Figure 17 and Figure 18.
When using a series dimFET to PWM dim the LED current,
more output capacitance is always better. A general rule of
thumb is to use a minimum of 40 µF when PWM dimming. For
most applications, this will provide adequate energy storage
at the output when the dimFET turns off and opens the LED
load. Then when the dimFET is turned back on, the capaci-
Even maintaining a dimming pulse greater than t_PULSE, pre-
serving linearity at low dimming duty cycles is difficult. Several
modifications are suggested for applications requiring low
dimming duty cycles. Since nDIM rising releases the latch but
does not trigger the on-time specifically, there will be an ef-
fective jitter on the rising edge of the LED current. This jitter
can be easily removed by tying the PWM input signal through
the synchronization network at the RT pin (shown in Figure
2), forcing the on-time to synchronize with the nDIM pulse.
The second helpful modification is to remove the C_FS capac-
itor and R_FS resistor, eliminating the high frequency compen-
sation pole. This should not affect stability, but it will speed up
the response of the CSH pin, specifically at the rising edge of
the LED current when PWM dimming, thus improving the
achievable linearity at low dimming duty cycles.
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FIGURE 17. Buck-boost Level-Shifted PWM Circuit
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FIGURE 18. Buck Level-Shifted PWM Circuit
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