COP880C Datasheet, PDF (17/31 Pages) National Semiconductor (TI) – Microcontrollers

Functional Description (Continued)
time into the timer, which continues to run. By alternately
loading in the on time and the off time at each successive
interrupt a PWM frequency can be easily generated.
DS010802-13
FIGURE 11. Timer Application
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE/PLUS control register contains
the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by
IEDG
External interrupt edge polarity select
(0 = rising edge, 1 = falling edge)
MSEL
Enable MICROWIRE/PLUS functions SO and
SK
TRUN
Start/Stop the Timer/Counter (1 = run, 0 = stop)
TC3
Timer input edge polarity select (0 = rising
edge, 1 = falling edge)
TC2
Selects the capture mode
TC1
Selects the timer mode
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
BIT
BIT
7
0
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE Global interrupt enable
ENI External interrupt enable
BUSY MICROWIRE/PLUS busy shifting
IPND External interrupt pending
ENTI Timer interrupt enable
TPND Timer interrupt pending
C
Carry Flag
HC Half carry Flag
HC C TPND ENTI IPND BUSY ENI GIE
BIT
BIT
7
0
Addressing Modes
REGISTER INDIRECT
This is the “normal” mode of addressing. The operand is the
memory addressed by the B register or X register.
DIRECT
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the
operand.
REGISTER INDIRECT
(AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically increments
or decrements the B or X register after executing the instruc-
tion.
RELATIVE
This mode is used for the JP instruction, the instruction field
is added to the program counter to get the new program
location. JP has a range of from −31 to +32 to allow a one
byte relative jump (JP + 1 is implemented by a NOP instruc-
tion). There are no “pages” when using JP, all 15 bits of PC
are used.
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
00 to 6F
70 to 7F
80 to BF
C0 to
CF
D0 to
DF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD–DF
E0 to EF
E0–E7
E8
E9
EA
EB
EC
ED
EE
EF
F0 to FF
FC
FD
Contents
On Chip RAM Bytes
Unused RAM Address Space (Reads as all Ones)
Expansion Space for future use
Expansion Space for I/O and Registers
On Chip I/O and Registers
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
On Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE/PLUS Shift Register
Timer Lower Byte
Timer Upper Byte
Timer Autoload Register Lower Byte
Timer Autoload Register Upper Byte
CNTRL Control Register
PSW Register
On Chip RAM Mapped as Registers
X Register
SP Register
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