ADC14DS065 Datasheet, PDF (17/30 Pages) –

ADC14DS095 LVDS Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A = V_DR = +3.3V, Internal V_REF = +1.2V,
f_CLK = 95 MHz, V_CM = V_CMO, C_L = 5 pF/pin. Typical values are for T_A = 25°C. Timing measurements are taken at 50% of the signal
amplitude. Boldface limits apply for T_MIN ≤ T_A ≤ T_MAX. All other limits apply for T_A = 25°C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10) ^Limits
Units
(Limits)
LVDS DC CHARACTERISTICS
V_OD
Output Differential Voltage
(SDO+) - (SDO-)
R_L = 100Ω
350
250
mV (min)
450
mV (max)
delta
V_OD
V_OS
Output Differential Voltage Unbalance R_L = 100Ω
Offset Voltage
R_L = 100Ω
±25
mV (max)
1.25
1.125
1.375
V (min)
V (max)
delta V_OS Offset Voltage Unbalance
R_L = 100Ω
IOS
Output Short Circuit Current
DO = 0V, V_IN = 1.1V,
LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS
±25
mV (max)
-10
mA (max)
t_DP
Output Data Bit Period
Single-Lane Mode
Dual-Lane Mode
0.75
ns
1.5
t_HO
Output Data Edge to Output Clock Edge Single-Lane Mode
Hold Time (Note 13)
Dual-Lane Mode
175
550
ps
t_SUO
Output Data Edge to Output Clock Edge Single-Lane Mode
Set-Up Time (Note 13)
Dual-Lane Mode
175
550
ps
t_FP
Frame Period
Single-Lane Mode
Dual-Lane Mode
10.53
21.05
ns
t_FDC
Frame Clock Duty Cycle (Note 13)
50
45
% (min)
55
% (max)
t_DFS
t_R, t_F
t_ODOR
Data Edge to Frame Edge Skew
LVDS Rise/Fall Time
Output Delay of OR output
50% to 50%
C_L=5pF to GND, R_OUT=100Ω
From rising edge of CLKL to ORA/ORB
valid
TBD
TBD
4
ps (max)
ps (max)
ns
t_DLD
Serializer DLL Lock Time
t_SD
Serializer Delay
R_L=100Ω
TBD
µs
TBD
ns
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