ADC14DS065 Datasheet, PDF (1/30 Pages) –

ADVANCE INFORMATION
February 2007
ADC14DS065/ADC14DS080/ADC14DS095/ADC14DS105
Dual 14-Bit, 65/80/95/105 MSPS A/D Converter with Serial
LVDS Outputs
General Description
NOTE: This is Advance Information for products current-
ly in development. ALL specifications are design targets
and are subject to change.
The ADC14DS065, ADC14DS080, ADC14DS095, and AD-
C14DS105 are high-performance CMOS analog-to-digital
converters capable of converting two analog input signals into
14-bit digital words at rates up to 65/80/95/105 Mega Samples
Per Second (MSPS) respectively. The digital outputs are se-
rialized and provided on differential LVDS signal pairs. These
converters use a differential, pipelined architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize power consumption and the external component
count, while providing excellent dynamic performance. A
unique sample-and-hold stage yields a full-power bandwidth
of 1 GHz. The ADC14DS065/080/095/105 may be operated
from a single +3.3V power supply. A power-down feature re-
duces the power consumption to very low levels while still
allowing fast wake-up time to full operation. The differential
inputs provide a 2V full scale differential input swing. A stable
1.2V internal voltage reference is provided, or the AD-
C14DS065/080/095/105 can be operated with an external
1.2V reference. Output data format (offset binary versus 2's
complement) and duty cycle stabilizer are pin-selectable. The
duty cycle stabilizer maintains performance over a wide range
of clock duty cycles.
The ADC14DS065/080/095/105 is available in a 60-lead LLP
package and operates over the industrial temperature range
of −40°C to +85°C.
Features
■ ^{1 GHz Full Power Bandwidth}
■ ^{Internal sample-and-hold circuit and precision reference}
■ ^{Low power consumption}
■ ^{Clock Duty Cycle Stabilizer}
■ ^{Single +3.3V supply operation}
■ ^{Offset binary or 2's complement output data format}
■ ^{Serial LVDS Outputs}
■ ^{60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)}
Key Specifications
■ ^{For ADC14DS105}
■ ^Resolution
■ ^{Conversion Rate}
■ ^{SNR (f}_IN ^{= 240 MHz)}
■ ^{SFDR (f}_IN ^{= 240 MHz)}
■ ^{Full Power Bandwidth}
■ ^{Power Consumption}
14 Bits
105 MSPS
72 dBFS (typ)
83 dBFS (typ)
1 GHz (typ)
1060 mW (typ)
Applications
■ ^{High IF Sampling Receivers}
■ ^{Wireless Base Station Receivers}
■ ^{Test and Measurement Equipment}
■ ^{Communications Instrumentation}
■ ^{Portable Instrumentation}
Connection Diagram
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