ADC14071 Datasheet, PDF (16/18 Pages) National Semiconductor (TI) – 14-Bit, 7 MSPS, 380 mW A/D Converter

Applications Information (Continued)
relatively low impedance across this narrow ground connec-
tion. This implies that the power supply ground should be
connected to the digital ground plane.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep any clock line
as short as possible and isolated from ALL other lines, in-
cluding other digital lines. Even the generally accepted 90˚
crossing should be avoided as even a little coupling can
cause problems at high frequencies. This is because other
lines can introduce phase noise (jitter) into the clock line,
which can lead to degradation of SNR. Also, the high speed
clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual in-
ductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected be-
tween the converter’s input pins and ground or to the refer-
ence pin and ground should be connected to a very clean
point in the analog ground plane.
Figure 8 gives an example of a suitable layout. All analog cir-
cuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog ground plane. All digital cir-
cuitry and I/O lines should be placed over the digital ground
plane. Furthermore, all components in the reference circuitry
and the input signal chain that are connected to ground
should be connected together with traces and enter the ana-
log ground plane at a single point.
All ground connections should have a low inductance path to
ground.
FIGURE 8. Example of A Suitable Layout
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance with the
ADC14071, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolate the ADC clock
from any digital circuitry with buffers, as with the clock tree
shown in Figure 9.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce phase
noise (jitter) into the clock signal, which can lead to reduced
SNR performance, and the clock can introduce noise into
other lines. Even lines with 90˚ crossings have capacitive
coupling, so try to avoid even these 90˚ crossings of the
clock line.
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DS101101-28