LMX3160 Datasheet, PDF (15/16 Pages) National Semiconductor (TI) – Single Chip Radio Transceiver

A plot of the magnitude and phase of G(s)H(s) for a stable
loop is shown in Figure 4 with a solid trace The parameter
w_p shows the amount of phase margin that exists at the
point the gain drops below zero (the cutoff frequency wp of
the loop) In a critically damped system the amount of
phase margin would be approximately 45
If we were now to redefine the cut off frequency 0_p as
double the frequency which gave us our original loop band-
width wp the loop response time would be approximately
halved Because the filter attenuation at the comparison fre-
quency also diminishes the spurs would have increased by
approximately 6 dB In the proposed FastLock scheme the
higher spur levels and wider loop filter conditions would ex-
ist only during the initial lock-on phase just long enough to
reap the benefits of locking faster The objective would be
to open up the loop bandwidth but not introduce any addi-
tional complications or compromises related to our original
design criteria We would ideally like to momentarily shift the
curve of Figure 4 over to a different cutoff frequency illus-
trated by the dotted line without affecting the relative open
loop gain and phase relationships To maintain the same
gain phase relationship at twice the original cutoff frequen-
cy other terms in the gain and phase equations 4 and 5 will
have to compensate by the corresponding ‘‘1 0’’ or ‘‘1 0²â€™â€™
factor Examination of equations 3 and 5 indicates the
damping resistor variable R2 could be chosen to compen-
sate the ‘‘0’’ terms for the phase margin This implies that
another resistor of equal value to R2 will need to be
switched in parallel with R2 during the initial lock period We
must also insure that the magnitude of the open loop gain
H(s)G(s) is equal to zero at 0_p e 2 0_p K_vco K_w N or the
net product of these terms can be changed by a factor of 4
to counteract the 0² term present in the denominator of
Equation 3 The Kw term was chosen to complete the trans-
formation because it can readily be switched between 1X
and 4X values This is accomplished by increasing the
charge pump output current from 1 5 mA in the standard
mode to 6 mA in FastLock
FastLock Circuit Implementation
A diagram of the FastLock scheme as implemented in Na-
tional Semiconductors LMX3160 is shown in Figure 5 When
a new frequency is loaded the charge pump circuit receives
an input to deliver 4 times the normal current per unit phase
error while an open drain NMOS on chip device switches in
a second R2 resistor element to ground The user calcu-
lates the loop filter component values for the normal steady
state considerations The device configuration ensures that
as long as a second identical damping resistor is wired in
appropriately the loop will lock faster without any additional
stability considerations to account for Once locked on the
correct frequency the PLL will then return to standard low
noise operation This transition does not affect the charge
on the loop filter capacitors and is enacted synchronous
with the charge pump output This creates a nearly seam-
less change between FastLock and standard mode
Figure 4 Open Loop Response Bode Plot
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FIGURE 5 FastLock PLL Architecture
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