LMH6550_06 Datasheet, PDF (15/17 Pages) National Semiconductor (TI) – Differential, High Speed Op Amp

Application Section (Continued)
NOTE: If V_CM is not 0V then there will be quiescent current
flowing in the feedback network. This current should be
included in the thermal calculations and added into the qui-
escent power dissipation of the amplifier.
ESD PROTECTION
The LMH6550 is protected against electrostatic discharge
(ESD) on all pins. The LMH6550 will survive 2000V Human
Body model and 200V Machine model events. Under normal
operation the ESD diodes have no effect on circuit perfor-
mance. There are occasions, however, when the ESD di-
odes will be evident. If the LMH6550 is driven by a large
signal while the device is powered down the ESD diodes will
conduct . The current that flows through the ESD diodes will
either exit the chip through the supply pins or will flow
through the device, hence it is possible to power up a chip
with a large signal applied to the input pins. Using the
shutdown mode is one way to conserve power and still
prevent unexpected operation.
BOARD LAYOUT
The LMH6550 is a very high performance amplifier. In order
to get maximum benefit from the differential circuit architec-
ture board layout and component selection is very critical.
The circuit board should have low a inductance ground plane
and well bypassed broad supply lines. External components
should be leadless surface mount types. The feedback net-
work and output matching resistors should be composed of
short traces and precision resistors (0.1%). The output
matching resistors should be placed within 3-4 mm of the
amplifier as should the supply bypass capacitors. The
LMH730154 evaluation board is an example of good layout
techniques. Evaluation boards are available free of charge
through the product folder on National’s web site.
The LMH6550 is sensitive to parasitic capacitances on the
amplifier inputs and to a lesser extent on the outputs as well.
Ground and power plane metal should be removed from
beneath the amplifier and from beneath R_F and R_G.
With any differential signal path symmetry is very important.
Even small amounts of assymetery will contribute to distor-
tion and balance errors.
EVALUATION BOARD
Generally, a good high frequency layout will keep power
supply and ground traces away from the inverting input and
output pins. Parasitic capacitances on these nodes to
ground will cause frequency response peaking and possible
circuit oscillations (see Application Note OA-15 for more
information). National Semiconductor suggests the following
evaluation boards as a guide for high frequency layout and
as an aid in device testing and characterization:
Device
LMH6550MA
Package
SOIC
Evaluation Board
Part Number
LMH730154
These evaluation boards can be shipped when a device
sample request is placed with National Semiconductor.
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