SCAN926260 Datasheet, PDF (14/18 Pages) National Semiconductor (TI) – Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST

Application Information (Continued)
PVDD = PLL SECTION POWER SUPPLY
The PVDD pin supplies the PLL circuit. PLL circuits require
clean power for the minimization of jitter. A supply noise
frequency in the 300kHZ to 1MHz range can cause in-
creased output jitter. Certain power supplies may have
switching frequencies or high harmonic content in this range.
If this is the case, filtering of this noise spectrum may be
required. A notch filter response is best to provide a stable
VDD, suppression of the noise band, and good high-
frequency response (clock fundamental). This may be ac-
complished with a pie filter (CRC or CLC). If employed, a
separate pie filter is recommended for each PLL to minimize
drop in potential due to the series resistance. Separate
power planes for the PVDD pins is typically not required.
AVDD = LVDS SECTION POWER SUPPLY
The AVDD pin supplies the LVDS portion of the circuit. The
SCAN926260 has four AVDD pins. Due to the nature of the
design, current draw is not excessive on these pins. A 0.1uF
capacitor is sufficient for these pins. If space is available, the
0.01uF capacitor may be used in parallel with the 0.1uF
capacitor for additional high frequency filtering.
GROUNDs
The AGND pin should be connected to the signal common in
the cable for the return path of any common-mode current.
Most of the LVDS current will be odd-mode and return within
the interconnect pair. A small amount of current may be
even-mode due to coupled noise and driver imbalances.
This current should return via a low impedance known path.
For a typical application circuit, please see Figure 10.
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FIGURE 10. Typical Application Circuit
(Only one power/ground for each supply type shown for clarity-bypass networks should be repeated for all
power/ground pairs.)
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FIGURE 11. Optional Additional External Failsafe Biasing
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