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LM3409 Datasheet, PDF (14/30 Pages) National Semiconductor (TI) – PFET Buck Controller for High Power LED Drives
INPUT CAPACITORS
Input capacitors are selected using requirements for mini-
mum capacitance and RMS ripple current. The PFET current
during tON is approximately ILED, therefore the input capacitors
discharge the difference between ILED and the average input
current (IIN) during tON. During tOFF, the input voltage source
charges up the input capacitors with IIN. The minimum input
capacitance (CIN-MIN) is selected using the maximum input
voltage ripple (ΔvIN-MAX) which can be tolerated. ΔvIN-MAX is
equal to the change in voltage across CIN during tON when it
supplies the load current. A good starting point for selection
of CIN is to use ΔvIN-MAX of 2% to 10% of VIN. CIN-MIN can be
selected as follows:
An input capacitance at least 75% greater than the calculated
CIN-MIN value is recommended. To determine the RMS input
current rating (IIN-RMS) the following approximation can be
used:
Since this approximation assumes there is no inductor ripple
current, the value should be increased by 10-30% depending
on the amount of ripple that is expected. Ceramic capacitors
are the best choice for input capacitors for the same reasons
mentioned in the Buck Converters with Output Capacitors
section. Careful selection of the capacitor requires checking
capacitance ratings at the nominal operating voltage and tem-
perature.
P-CHANNEL MosFET (PFET)
The LM3409/09HV requires an external PFET (Q1) as the
main power MosFET for the switching regulator. Q1 should
have a voltage rating at least 15% higher than the maximum
input voltage to ensure safe operation during the ringing of
the switch node. In practice all switching converters have
some ringing at the switch node due to the diode parasitic
capacitance and the lead inductance. The PFET should also
have a current rating at least 10% higher than the average
transistor current (IT):
The power rating is verified by calculating the power loss
(PT) using the RMS transistor current (IT-RMS) and the PFET
on-resistance (RDS-ON):
It is important to consider the gate charge of Q1. As the input
voltage increases from a nominal voltage to its maximum in-
put voltage, the COFT architecture will naturally increase the
switching frequency. The dominant switching losses are de-
termined by input voltage, switching frequency, and PFET
total gate charge (Qg). The LM3409/09HV has to provide and
remove charge Qg from the input capacitance of Q1 in order
to turn it on and off. This occurs more often at higher switching
frequencies which requires more current from the internal
regulator, thereby increasing internal power dissipation and
eventually causing the LM3409/09HV to thermally cycle. For
a given range of operating points the only effective way to
reduce these switching losses is to minimize Qg.
A good rule of thumb is to limit Qg < 30nC (if the switching
frequency remains below 300kHz for the entire operating
range then a larger Qg can be considered). If a PFET with
small RDS-ON and a high voltage rating is required, there may
be no choice but to use a PFET with Qg > 30nC.
When using a PFET with Qg > 30nC, the bypass capacitor
(CF) should not be connected to the VIN pin. This will ensure
that peak current detection through RSNS is not affected by
the charging of the PFET input capacitance during switching,
which can cause false triggering of the peak detection com-
parator. Instead, CF should be connected from the VCC pin
to the CSN pin which will cause a small DC offset in VCST and
ultimately ILED, however it avoids the problematic false trig-
gering.
In general, the PFET should be chosen to meet the Qg spec-
ification whenever possible, while minimizing RDS-ON. This will
minimize power losses while ensuring the part functions cor-
rectly over the full operating range.
RE-CIRCULATING DIODE
A re-circulating diode (D1) is required to carry the inductor
current during tOFF. The most efficient choice for D1 is a
Schottky diode due to low forward voltage drop and near-zero
reverse recovery time. Similar to Q1, D1 must have a voltage
rating at least 15% higher than the maximum input voltage to
ensure safe operation during the ringing of the switch node
and a current rating at least 10% higher than the average
diode current (ID):
The power rating is verified by calculating the power loss
through the diode. This is accomplished by checking the typ-
ical diode forward voltage (VD) from the I-V curve on the
product datasheet and calculating as follows:
In general, higher current diodes have a lower VD and come
in better performing packages minimizing both power losses
and temperature rise.
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