LM3409 Datasheet, PDF (12/30 Pages) National Semiconductor (TI) – PFET Buck Controller for High Power LED Drives

FIGURE 7. LED Current i_LED(t) During EN Pin PWM Dimming
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PWM DIMMING USING THE EN PIN
The enable pin (EN) is a TTL compatible input for PWM dim-
ming of the LED. A logic low (below 0.5V) at EN will disable
the internal driver and shut off the current flow to the LED
array. While the EN pin is in a logic low state the support cir-
cuitry (driver, bandgap, V_CC regulator) remains active in order
to minimize the time needed to turn the LED array back on
when the EN pin sees a logic high (above 1.74V).
Figure 7 shows the LED current (i_LED(t)) during PWM dimming
where duty cycle (D_DIM) is the percentage of the dimming pe-
riod (T_DIM) that the PFET is switching. For the remainder of
T_DIM, the PFET is disabled. The resulting dimmed average
LED current (I_DIM-LED) is:
The LED current rise and fall times (which are limited by the
slew rate of the inductor as well as the delay from activation
of the EN pin to the response of the external PFET) limit the
achievable T_DIM and D_DIM. In general, dimming frequency
should be at least one order of magnitude lower than the
steady state switching frequency in order to prevent aliasing.
However, for good linear response across the entire dimming
range, the dimming frequency may need to be even lower.
HIGH VOLTAGE NEGATIVE BIAS REGULATOR
The LM3409/09HV contains an internal linear regulator where
the steady state VCC pin voltage is typically 6.2V below the
voltage at the VIN pin. The VCC pin should be bypassed to
the VIN pin with at least 1µF of ceramic capacitance connect-
ed as close as possible to the IC.
INPUT UNDER-VOLTAGE LOCKOUT (UVLO)
Under-voltage lockout is set with a resistor divider from V_IN to
GND and is compared against a 1.24V threshold as shown in
Figure 8. Once the input voltage is above the preset UVLO
rising threshold (and assuming the part is enabled), the inter-
nal circuitry becomes active and a 22µA current source at the
UVLO pin is turned on. This extra current provides hysteresis
to create a lower UVLO falling threshold. The resistor divider
is chosen to set both the UVLO rising and falling thresholds.
FIGURE 8. UVLO Circuit
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The turn-on threshold (V_TURN-ON) is defined as follows:
The hysteresis (V_HYS) is defined as follows:
LOW POWER SHUTDOWN
The LM3409/09HV can be placed into a low power shutdown
(typically 110µA) by grounding the EN terminal (any voltage
below 0.5V) until V_CC drops below the V_CC UVLO threshold
(typically 3.73V). During normal operation this terminal should
be tied to a voltage above 1.74V and below absolute maxi-
mum input voltage rating.
THERMAL SHUTDOWN
Internal thermal shutdown circuitry is provided to protect the
IC in the event that the maximum junction temperature is ex-
ceeded. The threshold for thermal shutdown is 160°C with 15°
C of hysteresis (both values typical). During thermal shut-
down the PFET and driver are disabled.
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