LMK03000 Datasheet, PDF (13/22 Pages) Texas Instruments – Precision Clock Conditioner

2.2.3 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output pin. In order for these delays to be active, the respective CLKoutX_MUX
(See 2.2.1) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed
delay of approximately 400 ps is incurred in addition to the delay shown in the table below.
CLKoutX_DLY[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Delay (ps)
0
150
300
450
600
750
900
1050
1200
1350
1500
1650
1800
1950
2100
2250
2.2.4 CLKoutX_EN bit -- Clock Output Enables
This bit controls whether each clock output is enabled or not. If the EN_CLKout_Global bit (See 2.4.4) is set to zero or if GOE pin
is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled.
CLKoutX_EN bit
Don't care
Don't care
0
1
EN_CLKout_Global bit
Don't care
0
Don't care
1
GOE pin
0
Don't care
Don't care
High
Clock X Output State
Disabled
Disabled
Disabled
Enabled
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