LMK03000 Datasheet, PDF (1/22 Pages) Texas Instruments – Precision Clock Conditioner

ADVANCE INFORMATION
November 2006
LMK03000/LMK03000C/LMK03001/LMK03001C
Precision Clock Conditioner with Integrated VCO
General Description
The LMK03000/LMK03000C/LMK03001/LMK03001C preci-
sion clock conditioners combine the functions of jitter clean-
ing/reconditioning, multiplication, and distribution of a refer-
ence clock. The devices integrate a Voltage Controlled
Oscillator (VCO), a high performance Integer-N Phase
Locked Loop (PLL), a partially integrated loop filter, three
LVDS, and five LVPECL clock output distribution blocks.
The VCO output is optionally accessible on the Fout port. In-
ternally, the VCO output goes through an Input Divider to feed
the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
Features
■ ^{Integrated VCO and Integer-N PLL}
■ ^{Two performance grades (12 kHz to 20 MHz)}
— LMK03000/LMK03001: Less than 800 fs RMS
— LMK03000C/LMK03001C: Less than 400 fs RMS
■ ^{Two VCO frequency plans}
— LMK03000/LMK03000C: 1185 to 1296 MHz
— LMK03001/LMK03001C: 1470 to 1570 MHz
■ ^{Clock output frequency range of 1 to 785 MHz}
■ ^{3 LVDS and 5 LVPECL clock outputs}
■ ^{Partially integrated loop filter}
■ ^{Dedicated divider and delay blocks on each clock output}
■ ^{Pin compatible family of clocking devices}
■ ^{3.15 to 3.45 V operation}
■ ^{Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)}
Target Applications
■ ^{Data Converter Clocking}
■ ^{SONET/SDH, DSLAM}
■ ^Networking
■ ^{Wireless Infrastructure}
■ ^Medical
■ ^{Test and Measurement}
■ ^{Military / Aerospace}
Functional Block Diagram
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