LMK02000 Datasheet, PDF (13/20 Pages) National Semiconductor (TI) – Precision Clock Conditioner with Integrated PLL

2.3 REGISTER R0 to R7
Registers R0 through R7 control the eight clock outputs. Reg-
ister R0 controls CLKout0, Register R1 controls CLKout1, and
so on. There is one additional bit in register R0 called RESET.
Aside from this, the functions of these bits are identical. The
X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be
from 0 to 7.
2.3.1 RESET Bit -- R0 only
This bit is only in register R0. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power on reset condition and there-
fore automatically clears this bit. If this bit is set, all other R0
bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
Bit Name
RESET
CLKoutX_MUX
CLKoutX_EN
CLKoutX_DIV
CLKoutX_DLY
DIV4
EN_CLKout_Global
POWERDOWN
PLL_CP_TRI
PLL_CP_POL
PLL_MUX
PLL_R
PLL_CP_GAIN
PLL_N
Default
Bit Value
Bit State
0 No reset, normal operation
0 Bypassed
0 Disabled
1 Divide by 2
0 0 ps
0
PDF ≤ 20 MHz
1 Normal - CLKouts normal
0 Normal - Device active
0 Normal - PLL active
0 Negative Polarity CP
0 Disabled
10 R divider = 10
0 100 uA
760 N divider = 760
Bit Description
Reset to power on defaults
CLKoutX mux mode
CLKoutX enable
CLKoutX clock divide
CLKoutX clock delay
Phase Detector Frequency
Global clock output enable
Device power down
TRI-STATE PLL charge pump
Polarity of charge pump
Multiplexer control for LD pin
PLL R divide value
Charge pump current
PLL N divide value
Register
Bit
Location
R0
31
18:17
16
R0 to R7
15:8
7:4
R11
15
27
26
25
R14
24
23:20
19:8
31:30
R15
25:8
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock
output. Changing between the different modes changes the
blocks in the signal path and therefore incurs a delay relative
to the bypass mode. The different MUX modes and associ-
ated delays are listed below.
CLKoutX_MUX
[1:0]
0
1
2
3
Mode
Added Delay
Relative to
Bypass Mode
Bypassed (default)
0 ps
Divided
100 ps
400 ps
Delayed
(In addition to the
programmed
delay)
500 ps
Divided and (In addition to the
Delayed
programmed
delay)
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