THS7530 Datasheet, PDF (12/24 Pages) Texas Instruments – HIGH-SPEED, FULLY DIFFERENTIAL, CONTINUOUSLY VARIABLE GAIN AMPLIFIER

THS7530
SLOS405C – DECEMBER 2002 – REVISED FEBRUARY 2010
1 kW
1 kW
V_S+ = 5 V
0.1 mF
0.1 mF
6.8 mF
49.9 W
49.9 W
0.1 mF
V_IN
V_CL+
V_CL-
V_OCM
PD
THS7530
0.1 mF
V_G-
V_{S- VG+}
33 pF
24.9 W
24.9 W
33 pF
V_OUT-
V_OUT+
Figure 23. DC-Coupled Single-Ended Input with
DC-Coupled Differential Output
1 kW
1 kW
V_S+ = 5 V
0.1 mF
0.1 mF
6.8 mF
V_IN+
24.9 W
24.9 W
V_CL+
V_CL-
33 pF
24.9 W
V_OCM
PD
THS7530
V_IN-
24.9 W
0.1 mF
V_G-
33 pF
V_{S- VG+}
V_OUT-
V_OUT+
Figure 24. DC-Coupled Differential Input with
DC-Coupled Differential Output
LAYOUT CONSIDERATIONS
The THS7530 comes in a thermally-enhanced
PowerPAD™ package. Figure 25 shows the
recommended number of vias and thermal land size
recommended for best performance. Thermal vias
connect the thermal land to internal or external
copper planes and should have a drill diameter
sufficiently small so that the via hole is effectively
plugged when the barrel of the via is plated with
copper. This plug is needed to prevent wicking the
solder away from the interface between the package
body and the thermal land on the surface of the
board during solder reflow. The experiments
conducted jointly with Solectron Texas indicate that a
via drill diameter of 0,33 mm (13 mils, or .013 in) or
smaller works well when 1-ounce copper is plated at
the surface of the board and simultaneously plating
the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a
solder mask material should be used to cap the vias
with a dimension equal to the via diameter + 0,1 mm
minimum. This prevents the solder from being wicked
through the thermal via and potentially creating a
solder void in the region between the package bottom
and the thermal land on the surface of the PCB.
TSSOP
14-Pin PWP Package
2´3
3.4
www.ti.com
5
Figure 25. Recommended Thermal Land Size and
Thermal Via Patterns (Dimensions in mm)
See TI's Technical Brief titled, PowerPAD™
Thermally Enhanced Package (SLMA002) for a
detailed discussion of the PowerPAD™ package, its
dimensions, and recommended use.
THEORY OF OPERATION
Figure 26 shows a simplified schematic of the
THS7530.
The input architecture is a modified Gilbert cell. The
output from the Gilbert cell is converted to a voltage
and buffered to the output as a fully-differential signal.
A summing node between the outputs is used to
compare the output common-mode voltage to the
V_OCM input. The V_OCM error amplifier then servos the
output common-mode voltage to maintain it equal to
the V_OCM input. Left unterminated, V_OCM is set to
midsupply by internal resistors.
The gain control input is conditioned to give
linear-in-dB gain control (block H). The gain control
input is a differential signal from 0 V to 0.9 V which
varies the gain from 11.6 dB to 46.5 dB.
V_CL+ and V_CL– provide inputs that limit the output
voltage swing of the amplifier.
V_CL+
V_CL-
V_S+
x1
Output
Buffer
V_OUT+
V_IN+
V_IN-
PD
V_S-
V_G+
V_G-
Power
Control
H
V_OCM Error
Amplifier
V_OUT-
V_OCM
THS7530
Figure 26. THS7530 Simplified Schematic
12
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