LP38853 Datasheet, PDF (12/18 Pages) Texas Instruments – LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start

V_OUT
0.8V
0.9V
1.0V
1.1V
1.2V
1.3V
1.4V
1.5V
1.6V
1.7V
1.8V
TABLE 1.
R1
R2
1.07 kΩ 1.78 kΩ
1.50 kΩ 1.87 kΩ
1.00 kΩ 1.00 kΩ
1.65 kΩ 1.37 kΩ
1.40 kΩ 1.00 kΩ
1.15 kΩ 715 Ω
1.07 kΩ 590 Ω
2.00 kΩ 1.00 kΩ
1.65 kΩ 750 Ω
2.55 kΩ 1.07 kΩ
2.94 kΩ 1.13 kΩ
C_FF
12 nF
8.2 nF
12 nF
8.2 nF
10 nF
12 nF
12 nF
6.8 nF
8.2 nF
5.6 nF
4.7 nF
F_Z
12.4 kHz
12.9 kHz
13.3 kHz
11.8 kHz
11.4 kHz
11.5 kHz
12.4 kHz
11.7 kHz
11.8 kHz
11.1 kHz
11.5 kHz
Please refer to Application Note AN-1378 for additional infor-
mation on how resistor tolerances affect the calculated V_OUT
value.
INPUT VOLTAGE
The input voltage (V_IN) is the high current external voltage rail
that will be regulated down to a lower voltage, which is applied
to the load. The input voltage must be at least V_OUT + V_DO,
and no higher than whatever value is used for V_BIAS.
For applications where V_BIAS is higher than 4.5V, V_IN must be
no greater than 4.5V, otherwise output voltage accuracy may
be affected.
BIAS VOLTAGE
The bias voltage (V_BIAS) is a low current external voltage rail
required to bias the control circuitry and provide gate drive for
the N-FET pass transistor. When V_OUT is set to 1.20V, or less,
V_BIAS may be anywhere in the operating range of 3.0V to 5.5V.
If V_OUT is set higher than 1.20V , V_BIAS must be between 4.5V
and 5.5V to ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
device from functioning when the bias voltage is below the
Under-Voltage Lock-Out (UVLO) threshold of approximately
2.45V.
As the bias voltage rises above the UVLO threshold the de-
vice control circuitry becomes active. There is approximately
150 mV of hysteresis built into the UVLO threshold to provide
noise immunity.
When the bias voltage is between the UVLO threshold and
the Minimum Operating Rating value of 3.0V the device will
be functional, but the operating parameters will not be within
the guaranteed limits.
SUPPLY SEQUENCING
There is no requirement for the order that V_IN or V_BIAS are
applied or removed.
One practical limitation is that the Soft-Start circuit starts
charging C_SS when both V_BIAS rises above the UVLO thresh-
old and the Enable pin is above the V_EN(ON) threshold. If the
application of V_IN is delayed beyond this point the benefits of
Soft-Start will be compromised.
In any case, the output voltage cannot be guaranteed until
both V_IN and V_BIAS are within the range of guaranteed oper-
ating values.
If used in a dual-supply system where the regulator output
load is returned to a negative supply, the output pin must be
diode clamped to ground. A Schottky diode is recommended
for this diode clamp.
REVERSE VOLTAGE
A reverse voltage condition will exist when the voltage at the
output pin is higher than the voltage at the input pin. Typically
this will happen when V_IN is abruptly taken low and C_OUT con-
tinues to hold a sufficient charge such that the input to output
voltage becomes reversed.
The NMOS pass element, by design, contains no body diode.
This means that, as long as the gate of the pass element is
not driven, there will not be any reverse current flow through
the pass element during a reverse voltage event. The gate of
the pass element is not driven when V_BIAS is below the UVLO
threshold, or when the Enable pin is held low.
When V_BIAS is above the UVLO threshold, and the Enable pin
is above the V_EN(ON) threshold, the control circuitry is active
and will attempt to regulate the output voltage. Since the input
voltage is less than the output voltage the control circuit will
drive the gate of the pass element to the full V_BIAS potential
when the output voltage begins to fall. In this condition, re-
verse current will flow from the output pin to the input pin ,
limited only by the R_DS(ON) of the pass element and the output
to input voltage differential. Discharging an output capacitor
up 1000 µF in this manner will not damage the device as the
current will rapidly decay. However, continuous reverse cur-
rent should be avoided.
SOFT-START
The LP38853 incorporates a Soft-Start function that reduces
the start-up current surge into the output capacitor (C_OUT) by
allowing V_OUT to rise slowly to the final value. This is accom-
plished by controlling V_REF at the SS pin. The soft-start timing
capacitor (C_SS) is internally held to ground until both V_BIAS
rises above the Under-Voltage Lock-Out threshold (ULVO)
and the Enable pin is higher than the V_EN(ON) threshold.
V_REF will rise at an RC rate defined by the internal resistance
of the SS pin (r_SS), and the external capacitor connected to
the SS pin. This allows the output voltage to rise in a con-
trolled manner until steady-state regulation is achieved. Typ-
ically, five time constants are recommended to assure that the
output voltage is sufficiently close to the final steady-state
value. During the soft-start time the output current can rise to
the built-in current limit.
Soft-Start Time = C_SS × r_SS × 5
(7)
Since the V_OUT rise will be exponential, not linear, the in-rush
current will peak during the first time constant (τ), and V_OUT
will require four additional time constants (4τ) to reach the final
value (5τ) .
After achieving normal operation, should either V_BIAS fall be-
low the ULVO threshold, or the Enable pin fall below the V_EN
(OFF) ^{threshold, the device output will be disabled and the Soft-}
Start capacitor (C_SS) discharge circuit will become active. The
C_SS discharge circuit will remain active until V_BIAS falls to 500
mV (typical). When V_BIAS falls below 500 mV (typical), the
C_SS discharge circuit will cease to function due to a lack of
sufficient biasing to the control circuitry.
Since V_REF appears on the SS pin, any leakage through C_SS
will cause V_REF to fall, and thus affect V_OUT. A leakage of 50
nA (about 10 MΩ) through C_SS will cause V_OUT to be approx-
imately 0.1% lower than nominal, while a leakage of 500 nA
(about 1 MΩ) will cause V_OUT to be approximately 1% lower
than nominal. Typical ceramic capacitors will have a factor of
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