LMC6492 Datasheet, PDF (12/18 Pages) National Semiconductor (TI) – CMOS Rail-to-Rail Input and Output Operational Amplifier

Application Notes (Continued)
DS012049-10
FIGURE 3. R_I Input Current Protection for
Voltages Exceeding the Supply Voltages
Rail-To-Rail Output
The approximate output resistance of the LMC6492/4 is
110Ω sourcing and 80Ω sinking at V_s = 5V. Using the calcu-
lated output resistance, maximum output voltage swing can
be esitmated as a function of load.
Compensating for Input Capacitance
It is quite common to use large values of feedback resis-
tance for amplifiers with ultra-low input current, like the
LMC6492/4.
Although the LMC6492/4 is highly stable over a wide range
of operating conditions, certain precautions must be met to
achieve the desired pulse response when a large feedback
resistor is used. Large feedback resistors with even small
values of input capacitance, due to transducers, photo-
diodes, and circuit board parasitics, reduce phase margins.
When high input impedances are demanded, guarding of the
LMC6492/4 is suggested. Guarding input lines will not only
reduce leakage, but lowers stray input capacitance as well.
(See Printed-Circuit-Board Layout for High Impedance
Work).
The effect of input capacitance can be compensated for by
adding a capacitor, C_f, around the feedback resistors (as in
Figure 1 ) such that:
or
R₁ C_IN ≤ R₂ C_f
Since it is often difficult to know the exact value of C_IN, C_f can
be experimentally adjusted so that the desired pulse re-
sponse is achieved. Refer to the LMC660 and LMC662 for a
more detailed discussion on compensating for input
capacitance.
DS012049-11
FIGURE 4. Cancelling the Effect of Input Capacitance
Capacitive Load Tolerance
All rail-to-rail output swing operational amplifiers have volt-
age gain in the output stage. A compensation capacitor is
normally included in this integrator stage. The frequency lo-
cation of the dominant pole is affected by the resistive load
on the amplifier. Capacitive load driving capability can be op-
timized by using an appropriate resistive load in parallel with
the capacitive load (see Typical Curves).
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole in the feedback loop is created by the
combination of the op-amp’s output impedance and the ca-
pacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an os-
cillatory or underdamped pulse response. With a few exter-
nal components, op amps can easily indirectly drive capaci-
tive loads, as shown in Figure 5.
DS012049-12
FIGURE 5. LMC6492/4 Noninverting Amplifier,
Compensated to Handle Capacitive Loads
Printed-Circuit-Board Layout
for High-Impedance Work
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6492/4, typically
150 fA, it is essential to have an excellent layout. Fortu-
nately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear accept-
ably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6492/4’s inputs and
the terminals of components connected to the op-amp’s in-
puts, as in Figure 6. To have a significant effect, guard rings
should be placed on both the top and bottom of the PC
board. This PC foil must then be connected to a voltage
which is at the same voltage as the amplifier inputs, since no
leakage current can flow between two points at the same po-
tential. For example, a PC board trace-to-pad resistance of
10¹²â„¦, which is normally considered a very large resistance,
could leak 5 pA if the trace were a 5V bus adjacent to the pad
of the input.
This would cause a 33 times degradation from the
LMC6492/4’s actual performance. If a guard ring is used and
held within 5 mV of the inputs, then the same resistance of
10¹¹â„¦ will only cause 0.05 pA of leakage current. See Figure
7 for typical connections of guard rings for standard op-amp
configurations.
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