COP413C Datasheet, PDF (12/16 Pages) National Semiconductor (TI) – Single-Chip CMOS Microcontrollers

COP413C Instruction Set (Continued)
TABLE III COP413C Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
TRANSFER OF CONTROL INSTRUCTIONS
JID
FF
x 1111 1111 ROM (PC₈ A M)
None
PC_{7 0}
JMP
a
x 6b
0110 000 a₈ a
PC
–
a_{7 0}
None
JP
a
–
1 a_{6 0}
x a
PC_{6 0}
(pages 2 3 only)
or
–
11 a_{5 0}
x a
PC_{5 0}
(all other pages)
None
Description
Jump Indirect (Note 2)
Jump
Jump within Page
(Note 1)
JSRP
JSR
RET
a
–
10 a_{5 0}
PC a 1 x SA x SB None
x 010
PC_{8 6}
x a
PC_{5 0}
a
x x 6b 0110 100 a₈ PC a 1 SA SB None
–
a_{7 0}
a x PC
48
0100 1000 SB x SA x PC
None
Jump to Subroutine Page
(Note 2)
Jump to Subroutine
Return from Subroutine
RETSK
49
0100 10011 SB x SA x PC
Always Skip on Return Return from Subroutine
then Skip
HALT
33
0011 0011
38
0011 1000
MEMORY REFERENCE INSTRUCTIONS
CAMQ
33
0011 0011
3C
0011 1100
CQMA
33
0011 0011
2C
0010 1100
LD
r
b5
00 r 0101
x A
Q_{7 4}
x RAM(B)
Q_{3 0}
x Q_{7 4} RAM(B)
x Q_{3 0} A
RAM(B) x A
x Br Z r
Br
None
None
None
None
Halt processor
Copy A RAM to Q
Copy Q to RAM A
Load RAM into A
Exclusive-OR Br with r
LQID
BF
x 1011 1111 ROM(PC₈ A M) Q None
SA x SB
Load Q Indirect
RMB
SMB
STII
0
4C
x 0100 1100 0 RAM(B)₀
1
45
x 0100 0101 0 RAM(B)₁
2
42
x 0100 0010 0 RAM(B)₂
3
43
x 0100 0011 0 RAM(B)₃
0
4D
x 0100 1101 1 RAM(B)₀
1
47
x 0100 0111 1 RAM(B)₁
2
46
x 0100 0110 1 RAM(B)₂
3
4B
x 0100 1011 1 RAM(B)₃
y
7b
0111 y
y x RAM(B)
Bd a 1 x Bd
None
None
None
Reset RAM Bit
Set RAM Bit
Store Memory Immediate
and Increment Bd
X
r
b6
00 r 0110 RAM(B)
A
None
x Br Z r
Br
Exchange RAM with A
Exclusive-OR Br with r
XAD
3 15
23
0010 0011 RAM(3 15)
A
BF
1011 1111
None
Exchange A with RAM
(3 15)
12