LP38500-ADJ Datasheet, PDF (11/16 Pages) National Semiconductor (TI) – 1.5A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs

RFI/EMI SUSCEPTIBILITY
RFI (Radio Frequency Interference) and EMI (Electro-Mag-
netic Interference) can degrade any integrated circuit's per-
formance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high frequen-
cy energy content (> 1 MHz), care must be taken to ensure
that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator
(such as applications where the input source comes from the
output of a switching regulator), good ceramic bypass capac-
itors must be used at the input pin of the IC to reduce the
amount of EMI conducted into the IC.
If the LP38500/2-ADJ output is connected to a load which
switches at high speed (such as a clock), the high-frequency
current pulses required by the load must be supplied by the
capacitors on the IC output. Since the bandwidth of the reg-
ulator loop is less than 300 kHz, the control circuitry cannot
respond to load changes above that frequency. This means
the effective output impedance of the IC at frequencies above
300 kHz is determined only by the output capacitor(s). Ce-
ramic capacitors provide the best performance in this type of
application.
In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. In such
cases, it is recommended that some inductance be placed
between the output capacitor and the load, and good RF by-
pass capacitors be placed directly across the load. PCB
layout is also critical in high noise environments, since RFI/
EMI is easily radiated directly into PC traces. Noisy circuitry
should be isolated from "clean" circuits where possible, and
grounded through a separate path. At MHz frequencies,
ground planes begin to look inductive and RFI/EMI can cause
ground bounce across the ground plane. In multi-layer PC
Board applications, care should be taken in layout so that
noisy power and ground planes do not radiate directly into
adjacent layers which carry analog power and ground.
OUTPUT NOISE
Noise is specified in two ways:
Spot Noise or Output noise density is the RMS sum of all
noise sources, measured at the regulator output, at a specific
frequency (measured with a 1Hz bandwidth). This type of
noise is usually plotted on a curve as a function of frequency.
Total output noise voltage or Broadband noise is the RMS
sum of spot noise over a specified bandwidth, usually several
decades of frequencies. Attention should be paid to the units
of measurement.
Spot noise is measured in units µV/√Hz or nV/√Hz and total
output noise is measured in µV(rms). The primary source of
noise in low-dropout regulators is the internal reference. In
CMOS regulators, noise has a low frequency component and
a high frequency component, which depend strongly on the
silicon area and quiescent current.
Noise can generally be reduced in two ways: increase the
transistor area or increase the reference current. However,
enlarging the transisitors will increase die size, and increasing
the reference current means higher total supply current
(ground pin current).
SHORT-CIRCUIT PROTECTION
The LP38500/2-ADJ contains internal current limiting which
will reduce output current to a safe value if the output is over-
loaded or shorted. Depending upon the value of V_IN, thermal
limiting may also become active as the average power dissi-
pated causes the die temperature to increase to the limit value
(about 170°C). The hysteresis of the thermal shutdown cir-
cuitry can result in a “cyclic” behavior on the output as the die
temperature heats and cools.
ENABLE OPERATION (LP38502-ADJ Only)
The Enable pin (EN) must be actively terminated by either a
10 kΩ pull-up resistor to V_IN, or a driver which actively pulls
high and low (such as a CMOS rail to rail comparator). If active
drive is used, the pull-up resistor is not required. This pin must
be tied to V_IN if not used (it must not be left floating).
DROPOUT VOLTAGE
The dropout voltage of a regulator is defined as the input-to-
output differential required by the regulator to keep the output
voltage within 2% of the nominal value. For CMOS LDOs, the
dropout voltage is the product of the load current and the
R_DS(on) of the internal MOSFET pass element.
Since the output voltage is beginning to “drop out” of regula-
tion when it drops by 2%, electrical performance of the device
will be reduced compared to the values listed in the Electrical
Characteristics table for some parameters (line and load reg-
ulation and PSRR would be affected).
REVERSE CURRENT PATH
The internal MOSFET pass element in the LP38500/2-ADJ
has an inherent parasitic diode. During normal operation, the
input voltage is higher than the output voltage and the para-
sitic diode is reverse biased. However, if the output is pulled
above the input in an application, then current flows from the
output to the input as the parasitic diode gets forward biased.
The output can be pulled above the input as long as the cur-
rent in the parasitic diode is limited to 200 mA continuous and
1A peak. The regulator output pin should not be taken below
ground potential. If the LP38500/2-ADJ is used in a dual-sup-
ply system where the regulator load is returned to a negative
supply, the output must be diode-clamped to ground.
POWER DISSIPATION/HEATSINKING
The maximum power dissipation (P_D(MAX)) of the LP38500/2-
ADJ is limited by the maximum junction temperature of
125°C, along with the maximum ambient temperature (T_A
(MAX)^{) of the application, and the thermal resistance (θ}JA^{) of}
the package. Under all possible conditions, the junction tem-
perature (T_J) must be within the range specified in the Oper-
ating Ratings. The total power dissipation of the device is
given by:
P_D = ((V_IN − V_OUT) x I_OUT) + (V_IN x I_GND)
(1)
where I_GND is the operating ground current of the device
(specified under Electrical Characteristics).
The maximum allowable junction temperature rise (ΔT_J) de-
pends on the maximum expected ambient temperature
(T_A(MAX)) of the application, and the maximum allowable junc-
tion temperature (T_J(MAX)):
ΔT_J = T_J(MAX)− T_A(MAX)
(2)
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ_JA, can be calculated using the formula:
θ_JA = ΔT_J / P_D(MAX)
(3)
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