LMH6704_14 Datasheet, PDF (11/20 Pages) National Semiconductor (TI) – MHz Selectable Gain Buffer with Disable

LMH6704
www.ti.com
SNOSAD0C – FEBRUARY 2005 – REVISED MARCH 2013
EVALUATION BOARDS
Texas Instruments provides the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the data sheet plots were measured with these boards.
Device
LMH6704MA
LMH6704MF
Package
SOIC-8
SOT23-6
Evaluation Board Part Number
CLC730227
CLC730216
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor R_ISO. Figure 23 shows
the use of a series output resistor, R_ISO, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
The chart “Suggested R_ISO vs. Cap Load” gives a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of R_ISO can be reduced slightly
from the recommended values.
V_IN
R_IN
50:
R_ISO
++
50:
--
CL
10 pF
V_OUT
R_L
1 k:
Figure 23. Decoupling Capacitive Loads
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. To reduce parasitic capacitances
ground and power planes should be removed near the input and output pins. For long signal paths controlled
impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors
should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in
pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic
capacitors should be placed as close to the device as possible. In Figure 17, Figure 18, and Figure 19 C_SS is
optional, but is recommended for best second order harmonic distortion. Another option to using C_SS is to use
pairs of 0.01 μF and 0.1 µF ceramic capacitors for each supply bypass.
V_IN
R_IN
75:
6.8 PF
C2
.01 PF
C1
++
--
R_OUT
75:
V_OUT
.01 PF
C3
6.8 PF
C4
Figure 24. Typical Video Application
Copyright © 2005–2013, Texas Instruments Incorporated
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