LM3475 Datasheet, PDF (11/14 Pages) National Semiconductor (TI) – Hysteretic PFET Buck Controller

Design Information (Continued)
The power loss in the PFET consists of switching losses and
conducting losses. Although switching losses are difficult to
precisely calculate, the equation below can be used to esti-
mate total power dissipation. Increasing R_DSON will increase
power losses and degrade efficiency. Note that switching
losses will also increase with lower gate threshold voltages.
PD_switch = R_DSONx (I_OUT)²x D + F x I_OUTx V_INx (t_on + t_off)/2
where:
t_on = FET turn on time
t_off = FET turn off time
A value of 10ns to 50ns is typical for ton and toff. Note that
the R_DSON has a positive temperature coefficient. At 100˚C,
the R_DSON may be as much as 150% higher than the value
at 25˚C.
The Gate capacitance of the PFET has a direct impact on
both PFET transition time and the power dissipation in the
LM3475. Most of the power dissipated in the LM3475 is used
to drive the PFET switch. This power can be calculated as
follows:
The amount of average gate driver current required during
switching (I_G) is:
I_G = Q_g x F
And the total power dissipated in the device is:
I_qV_IN + I_GV_IN
Where I_q is typically 260µA as shown in the Electrical Char-
acteristics table. As gate capacitance increases, operating
frequency may need to be reduced, or additional heat sink-
ing may be required to lower the power dissipation in the
device.
In general, keeping the gate capacitance below 2000pF is
recommended to keep transition times (switching losses),
and power losses low.
REDUCING SWITCHING NOISE
Although the LM3475 employs internal noise suppression
circuitry, external noise may continue to be excessive. There
are several methods available to reduce noise and EMI.
MOSFETs are very fast switching devices. The fast increase
in PFET current coupled with parasitic trace inductance can
create unwanted noise spikes at both the switch node and at
V_IN. Switching noise will increase with load current and input
voltage. This noise can also propagate through the ground
plane, sometimes causing unpredictable device perfor-
mance. Slowing the rise and fall times of the PFET can be
very effective in reducing this noise. Referring to Figure 4,
the PFET can be slowed down by placing a small (1Ω-10Ω)
resistor in series with PGATE. However, this resistor will
increase the switching losses in the PFET and will lower
efficiency. Therefore it should be kept as small as possible
and only used when necessary. Another method to reduce
switching noise (other than good PCB layout, see Layout
section) is to use a small RC filter or snubber. The snubber
should be placed in parallel with the catch diode, connected
close to the drain of the PFET, as shown in Figure 4. Again,
the snubber should be kept as small as possible to limit its
impact on system efficiency. A typical range is a 10Ω-100Ω
resistor and a 470pF to 2.2nF ceramic capacitor.
20070105
FIGURE 4. PGATE Resistor and Snubber
Layout
PC board layout is very important in all switching regulator
designs. Poor layout can cause EMI problems, excess
switching noise and poor operation.
As shown in Figure 6 and Figure 7, place the ground of the
input capacitor as close as possible to the anode of the
diode. This path also carries a large AC current. The switch
node, the node connecting the diode cathode, inductor, and
PFET drain, should be kept as small as possible. This node
is one of the main sources for radiated EMI.
The feedback pin is a high impedance node and is therefore
sensitive to noise. Be sure to keep all feedback traces away
from the inductor and the switch node, which are sources of
noise. Also, the resistor divider should be placed close to the
FB pin. The gate pin of the external PFET should be located
close to the PGATE pin.
Using a large, continuous ground plane is also recom-
mended, particularly in higher current applications.
11
www.national.com