LM3410_08 Datasheet, PDF (11/32 Pages) National Semiconductor (TI) – PowerWise® 525kHz/1.6MHz, Constant Current Boost and SEPIC LED Driver with Internal Compensation

of the capacitor’s reactance and its equivalent series resis-
tance (ESR):
When using MLCCs, the ESR is typically so low that the ca-
pacitive ripple may dominate. When this occurs, the output
ripple will be approximately sinusoidal and 90° phase shifted
from the switching action.
Given the availability and quality of MLCCs and the expected
output voltage of designs using the LM3410, there is really no
need to review any other capacitor technologies. Another
benefit of ceramic capacitors is their ability to bypass high
frequency noise. A certain amount of switching edge noise
will couple through parasitic capacitances in the inductor to
the output. A ceramic capacitor will bypass this noise while a
tantalum will not. Since the output capacitor is one of the two
external components that control the stability of the regulator
control loop, most applications will require a minimum at 0.47
µF of output capacitance. Like the input capacitor, recom-
mended multilayer ceramic capacitors are X7R or X5R.
Again, verify actual capacitance at the desired operating volt-
age and temperature.
DIODE
The diode (D1) conducts during the switch off time. A Schottky
diode is recommended for its fast switching times and low
forward voltage drop. The diode should be chosen so that its
current rating is greater than:
I_D1 ≥ I_OUT
The reverse breakdown rating of the diode must be at least
the maximum output voltage plus appropriate margin.
OUTPUT OVER-VOLTAGE PROTECTION
A simple circuit consisting of an external zener diode can be
implemented to protect the output and the LM3410 device
from an over-voltage fault condition. If an LED fails open, or
is connected backwards, an output open circuit condition will
occur. No current is conducted through the LED’s, and the
feedback node will equal zero volts. The LM3410 will react to
this fault by increasing the duty-cycle, thinking the LED cur-
rent has dropped. A simple circuit that protects the LM3410
is shown in figure 6.
Zener diode D2 and resistor R3 is placed from V_OUT in parallel
with the string of LEDs. If the output voltage exceeds the
breakdown voltage of the zener diode, current is drawn
through the zener diode, R3 and sense resistor R1. Once the
voltage across R1 and R3 equals the feedback voltage of
190mV, the LM3410 will limit its duty-cycle. No damage will
occur to the LM3410, the LED’s, or the zener diode. Once the
fault is corrected, the application will work as intended.
30038530
FIGURE 6. Overvoltage Protection Circuit
PCB Layout Considerations
When planning layout there are a few things to consider when
trying to achieve a clean, regulated output. The most impor-
tant consideration when completing a Boost Converter layout
is the close coupling of the GND connections of the C_OUT ca-
pacitor and the LM3410 PGND pin. The GND ends should be
close to one another and be connected to the GND plane with
at least two through-holes. There should be a continuous
ground plane on the bottom layer of a two-layer board except
under the switching node island. The FB pin is a high
impedance node and care should be taken to make the FB
trace short to avoid noise pickup and inaccurate regulation.
The R_SET feedback resistor should be placed as close as
possible to the IC, with the AGND of R_SET (R1) placed as close
as possible to the AGND (pin 5 for the LLP) of the IC. Radiated
noise can be decreased by choosing a shielded inductor. The
remaining components should also be placed as close as
possible to the IC. Please see Application Note AN-1229 for
further considerations and the LM3410 demo board as an ex-
ample of a four-layer layout.
Below is an example of a good thermal & electrical PCB de-
sign.
30038532
FIGURE 7. Boost PCB Layout Guidelines
This is very similar to our LM3410 demonstration boards that
are obtainable via the National Semiconductor website. The
demonstration board consists of a two layer PCB with a com-
mon input and output voltage application. Most of the routing
is on the top layer, with the bottom layer consisting of a large
ground plane. The placement of the external components
satisfies the electrical considerations, and the thermal perfor-
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