DS90CR218A Datasheet, PDF (11/15 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link - 85 MHz

AC Timing Diagrams (Continued)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 10) + ISI (Inter-symbol interference) (Note 11)
Cable Skew — typicaIIy 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 85MHz
Note 11: ISI is dependent on interconnect length; may be zero
FIGURE 17. Receiver LVDS Input Skew Margin
DS101080-20
Applications Information
The DS90CR217 and DS90CR218A are backward compat-
ible with the existing 5V Channel Link transmitter/receiver
pair (DS90CR213, DS90CR214). To upgrade from a 5V to a
3.3V system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the V_CC, LVDS V_CC and PLL V _CC.
2. Transmitter input and control inputs except 3.3V TTL/
CMOS levels. They are not 5V tolerant.
3. The receiver powerdown feature when enabled wilI lock
receiver output to a logic low. However, the 5V/66 MHz
receiver maintain the outputs in the previous state when
powerdown occurred.
DS90CR217 Pin Description — Channel Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O No.
Description
I
21 TTL level input.
O
3 Positive LVDS differential data output.
O
3 Negative LVDS differential data output.
I
1 TTL level clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 TTL level input. Assertion (low input) TRI-STATEs the outputs, ensuring low current at
power down.
I
4 Power supply pins for TTL inputs.
I
5 Ground pins for TTL inputs.
I
1 Power supply pins for PLL.
I
2 Ground pins for PLL.
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
DS90CR218A Pin Description — Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
I/O No.
Description
I
3 Positive LVDS differential data inputs.
I
3 Negative LVDS differential data inputs.
O 21 TTL level data outputs.
I
1 Positive LVDS differential clock input.
I
1 Negative LVDS differential clock input.
O
1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
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