DS25BR440 Datasheet, PDF (11/16 Pages) National Semiconductor (TI) – 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

Functional Description
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer opti-
mized for high-speed signal routing and repeating over lossy
FR-4 printed circuit board backplanes and balanced cables.
The DS25BR440 has a pre-emphasis control pin for each
output for switching the transmit pre-emphasis to ON and
Transmit Pre-emphasis Truth Table
OFF setting and an equalization control pin for each input for
switching the receive equalization to ON and OFF setting. The
following are the transmit pre-emphasis and receive equal-
ization truth tables.
OUTPUT OUTn, n = {0, 1, 2, 3}
CONTROL Pin (PEn) State
0
1
Pre-emphasis Level
OFF
ON
Transmit Pre-emphasis Level Selection for an Output OUTn
Receive Equalization Truth Table
CONTROL Pin (EQn) State
0
1
INPUT INn, n = {0, 1, 2, 3}
Receive Equalization Level Selection for an Input INn
Equalization Level
OFF
ON
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