DS25BR440 Datasheet, PDF (1/16 Pages) National Semiconductor (TI) – 3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

February 11, 2008
DS25BR440
3.125 Gbps Quad LVDS Buffer with Transmit Pre-Emphasis
and Receive Equalization
General Description
The DS25BR440 is a 3.125 Gbps Quad LVDS buffer opti-
mized for high-speed signal routing and repeating over lossy
FR-4 printed circuit board backplanes and balanced cables.
Fully differential signal paths ensure exceptional signal in-
tegrity and noise immunity.
The DS25BR440 features two levels of transmit pre-empha-
sis (PE) and two levels of receive equalization (EQ). Both of
these features compensate for interconnect losses and ulti-
mately maximize noise margin. A loss-of-signal (LOS) circuit
monitors each input channel and a unique LOS pin is asserted
when no signal is detected at that input
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device return losses,
reduce component count and further minimize board space.
Features
■ ^{DC - 3.125 Gbps low jitter, low skew, low power operation}
■ ^{Pin selectable transmit pre-emphasis and receive}
equalization eliminate data dependant jitter
■ ^{Wide input common mode voltage range allows DC-}
coupled interface to LVDS, CML and LVPECL drivers
■ ^{LOS circuitry detects open inputs fault}
■ ^{Integrated 100Ω input and output terminations}
■ ^{8 kV ESD on LVDS I/O pins protects adjoining}
components
■ ^{Small 6 mm x 6 mm LLP-40 space saving package}
Applications
■ ^{Clock and data buffering and repeating}
■ ^{Copper cable driving and equalization}
■ ^{FR-4 equalization}
■ ^{OC-48 / STM-16}
Typical Application
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