CD4046BC Datasheet, PDF (11/14 Pages) Fairchild Semiconductor – Micropower Phase-Locked Loop

Design Information
This information is a guide for approximating the value of
external components for the CD4046B in a phase-locked-
loop system The selected external components must be
within the following ranges R1 R2 ^t 10 kX R_S ^t 10 kX
C1 ^t 50 pF
In addition to the given design information refer to Figure 5
for R1 R2 and C1 component selections
Characteristics
VCO Frequency
Using Phase Comparator I
VCO Without Offset
R2 e %
VCO With Offset
Using Phase Comparator II
VCO Without Offset
R2 e %
VCO With Offset
For No Signal Input
Frequency Lock
Range 2 f_L
Frequency Capture
Range 2 f_C
Loop Filter
Component
Selection
TL F 5968–7
TL F 5968 – 8
TL F 5968 – 9
TL F 5968 – 10
VCO in PLL system will adjust
to center frequency f_o
VCO in PLL system will adjust to
lowest operating frequency f_min
2 f_L e full VCO frequency range
2 f_L e f_max b f_min
TL F 5968–11
0 ^{2 fC}
1 2 q f_L
q u1
For 2 f_C see Ref
f_C e f_L
TL F 5968–12
Phase Angle Between
Single and Comparator
Locks on Harmonics
of Center Frequency
Signal Input Noise
Rejection
90 at center frequency (f_o) approximating
0 and 180 at ends of lock range (2 f_L)
Yes
High
Always 0 in lock
No
Low
VCO Component
Selection
Given f_o
Use f_o with
Figure 5a to
determine R1
and C1
Given f_o and f_L
Calculate f_min
from the equation
f_min e f_o b f_L
Use f_min with Figure 5b
to determine R2 and C1
Calculate ^fmax
f_min
from the equation
f_{max e} f_o a f_L
f_min f_o b f_L
Use ^fmax with Figure 5c
f_min
to determine ratio R2
R1 to obtain R1
Given f_max
Calculate f_o from
the equation
f_o
e
f_max
2
Use f_o with Figure 5a to
determine R1 and C1
Given f_min and f_max
Use f_min with
Figure 5b to
determine R2 and C1
Calculate ^fmax
f_min
Use ^fmax with Figure 5c
f_min
to determine ratio
R2 R1 to obtain R1
References
G S Moschytz ‘‘Miniaturized RC Filters Using Phase-Locked Loop’’ BSTJ May 1965
Floyd Gardner ‘‘Phaselock Techniques’’ John Wiley Sons 1966
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