DS90CF583 Datasheet, PDF (10/12 Pages) National Semiconductor (TI) – LVDS 24-Bit Color Flat Panel Display (FPD) Link─ 65 MHz

AC Timing Diagrams (Continued)
FIGURE 16. Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF583)
DS012616-18
FIGURE 17. Receiver Powerdown Delay
DS012616-21
DS012616-22
FIGURE 18. Transmitter Powerdown Delay
DS90CF583 Pin Descriptions — FPD Link Transmitter
Pin Name
TxIN
I/O No.
I 28
TxOUT+
O4
TxOUT−
O4
FPSHIFT IN
I
1
TxCLK OUT+ O 1
TxCLK OUT− O 1
PWR DOWN
I
1
V_CC
I
4
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME, DRDY and CNTL (also referred to as HSYNC, VSYNC, Data Enable, CNTL)
Positive LVDS differential data output
Negative LVDS differential data output
TTL level clock input. The falling edge acts as data strobe
Positive LVDS differential clock output
Negative LVDS differential clock output
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down
Power supply pins for TTL inputs
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