DS90CF583 Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – LVDS 24-Bit Color Flat Panel Display (FPD) Link─ 65 MHz

November 1996
DS90CF583/DS90CF584
LVDS 24-Bit Color Flat Panel Display (FPD) Link—
65 MHz
General Description
The DS90CF583 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CF584 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 65 MHz, 24 bits of RGB data and 4
bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY, CONTROL) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data through-
put is 227 Mbytes per second. These devices are offered
with falling edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clk support
n Up to 227 Mbytes/s bandwidth
n Cable size is reduced to save cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design (< 550 mW typ)
n Power-down mode saves power (< 0.25 mW)
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Falling edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Single pixel per clock XGA (1024 x 768)
n Supports VGA, SVGA, XGA and higher
n 1.8 Gbps throughput
Block Diagrams
DS012616-24
Order Number DS90CF583MTD
See NS Package Number MTD56
DS012616-1
Order Number DS90CF584MTD
See NS Package Number MTD56
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© 1998 National Semiconductor Corporation DS012616
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