PC87415 Datasheet, PDF (1/42 Pages) National Semiconductor (TI) – PCI-IDE DMA Master Mode Interface Controller

PRELIMINARY
March 1996
PC87415
PCI-IDE DMA Master Mode Interface Controller
1 0 General Description
The Enhanced PCI-IDE Interface is a single-chip controller
packaged in a 100-pin PQFP It provides 2 IDE channels for
interfacing up to 4 IDE drives or 2 IDE drives and CD-ROM
directly on the PCI Local bus An enhanced DMA controller
on-chip increases system performance by providing full
scatter gather data transfers between IDE devices and sys-
tem memory without CPU intervention Four levels of both
write posting and read prefetching per channel allow the
host CPU to run concurrently with IDE cycles Programma-
ble timing functions provide maximum flexibility of timing pa-
rameters per drive for optimizing the data transfer rate per
drive Both PC compatible addressing and PCI compliant
addressing are supported by re-mapping the base address-
es A power control feature allows turning off power to the
IDE cables
The Enhanced PCI-IDE Interface connection to the PCI bus
is virtually ‘‘glue-less’’ with only one additional TTL data
buffer (optional) This high-integration solution reduces
component count eases board design reduces cost and
increases reliability
The Enhanced PCI-IDE supports faster ATA devices using
PIO modes 1 2 3 and 4 as well as DMA modes 0 1 and 2
It comes with a full suite of software drivers for DOS 5 0 –
6 x Windows 3 x Windows 95 Windows NT^TM OS 2
2 x Novell NetWare^TM 3 1x – 4 x and SCO UNIX 3 x
TRI-STATE is a registered trademark of National Semiconductor Corporation
WATCHDOGTM is a trademark of National Semiconductor Corporation
Novell is a registered trademark of Novell Inc
NetWareTM is a trademark of Novell Inc
Unix is a registered trademark of AT T Bell Laboratories
Windows and Windows 95 are registered trademarks of Microsoft Corporation
Windows NTTM is a trademark of Microsoft Corporation
2 0 Features
Y _{PCI bus interface for up to 4 IDE devices}
Y _{33 MHz 32-bit PCI bus data path with full parity error}
reporting
Y _{16 7 MByte sec maximum IDE transfer rate}
Y _{Support for 2 IDE channels ( 2 IDE devices per chan-}
nel)
Y _{Primary or secondary IDE addressing (1F0x 170x) in}
PC compatible mode
Y _{Re-mappable base registers for full PCI compliance}
Y _{Concurrent channel operation (PIO DMA modes)}
Y _{4 Double Word write FIFO per channel}
Y _{4 Double Word read prefetch FIFO per channel}
Y _{Enhanced DMA mode with scatter gather capability}
Y _{ANSI ATA Modes 0 through 4 PIO support (internal}
DMA not selected)
Y _{IORDY handshaking for PIO}
Y _{ANSI ATA Modes 0 through 2 Multiword DMA support}
(internal DMA selected)
Y _{Individually programmable command and recovery tim-}
ing for reads and writes per channel drive for com-
mand control and data
Y _{Individually programmable data sector size for read pre-}
fetches per channel
Y _{PC compatible interrupt routing of IRQ14 and IRQ15}
Y _{Hardware and software chip enable disable}
Y _{Optional Power Control for IDE Drives}
Y _{Fully static logic design}
Y _{100-pin PQFP package}
FIGURE 1 The PC87415 in a PCI Based System
C1996 National Semiconductor Corporation TL F 12497
RRD-B30M46 Printed in U S A
TL F 12497 – 1
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