DS90LV048A Datasheet, PDF (1/11 Pages) National Semiconductor (TI) – 3V LVDS Quad CMOS Differential Line Receiver

July 1999
DS90LV048A
3V LVDS Quad CMOS Differential Line Receiver
General Description
The DS90LV048A is a quad CMOS flow-through differential
line receiver designed for applications requiring ultra low
power dissipation and high data rates. The device is de-
signed to support data rates in excess of 400 Mbps (200
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The DS90LV048A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS out-
put levels. The receiver supports a TRI-STATE^® function that
may be used to multiplex outputs. The receiver also supports
open, shorted and terminated (100Ω) input fail-safe. The re-
ceiver output will be HIGH for all fail-safe conditions. The
DS90LV048A has a flow-through pinout for easy PCB layout.
The EN and EN* inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four re-
ceivers. The DS90LV048A and companion LVDS line driver
(eg. DS90LV047A) provide a new alternative to high power
PECL/ECL devices for high speed point-to-point interface
applications.
Features
n >400 Mbps (200 MHz) switching rates
n Flow-through pinout simplifies PCB layout
n 150 ps channel-to-channel skew (typical)
n 100 ps differential skew (typical)
n 2.7 ns maximum propagation delay
n 3.3V power supply design
n High impedance LVDS inputs on power down
n Low Power design (40mW 3.3V static)
n Interoperable with existing 5V LVDS drivers
n Accepts small swing (350 mV typical) differential signal
levels
n Supports open, short and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 Standard
n Industrial temperature operating range (-40˚C to +85˚C)
n Available in SOIC and TSSOP package
Connection Diagram
Dual-in-Line
Functional Diagram
DS100888-1
Order Number DS90LV048ATM, DS90LV048ATMTC
See NS Package Number M16A, MTC16
DS100888-2
ENABLES
EN
EN*
H
L or Open
All other combinations of ENABLE inputs
INPUTS
R_IN+ − R_IN−
V_ID ≥ 0.1V
V_ID ≤ −0.1V
Full Fail-safe
OPEN/SHORT
or Terminated
X
OUTPUT
R_OUT
H
L
H
Z
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100888
www.national.com