DS90LV032A Datasheet, PDF (1/9 Pages) National Semiconductor (TI) – 3V LVDS Quad CMOS Differential Line Receiver

July 1999
DS90LV032A
3V LVDS Quad CMOS Differential Line Receiver
General Description
The DS90LV032A is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 400 Mbps (200 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The DS90LV032A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS out-
put levels. The receiver supports a TRI-STATE^® function that
may be used to multiplex outputs. The receiver also supports
open, shorted and terminated (100Ω) input Fail-safe. The re-
ceiver output will be HIGH for all fail-safe conditions.
The DS90LV032A and companion LVDS line driver (eg.
DS90LV031A) provide a new alternative to high power
PECL/ECL devices for high speed point-to-point interface
applications.
Features
n >400 Mbps (200 MHz) switching rates
n 0.1 ns channel-to-channel skew (typical)
n 0.1 ns differential skew (typical)
n 3.3 ns maximum propagation delay
n 3.3V power supply design
n Power down high impedance on LVDS inputs
n Low Power design (40mW 3.3V static)
n Interoperable with existing 5V LVDS networks
n Accepts small swing (350 mV typical) VID
n Supports open, short and terminated input fail-safe
n Compatible with ANSI/TIA/EIA-644
n Industrial temp. operating range (-40˚C to +85˚C)
n Available in SOIC and TSSOP Packaging
Connection Diagram
Dual-in-Line
Functional Diagram
DS100067-1
Order Number DS90LV032ATM
or DS90LV032ATMTC
See NS Package Number M16A or MTC16
ENABLES
EN
EN*
L
H
All other combinations
of ENABLE inputs
INPUTS
R_IN+ − R_IN−
X
V_ID ≥ 0.1V
V_ID ≤ −0.1V
Full Fail-safe
OPEN/SHORT
or Terminated
OUTPUT
R_OUT
Z
H
L
H
DS100067-2
© 1999 National Semiconductor Corporation DS100067
www.national.com