DS90C032 Datasheet, PDF (1/12 Pages) National Semiconductor (TI) – LVDS Quad CMOS Differential Line Receiver

September 2003
DS90C032
LVDS Quad CMOS Differential Line Receiver
General Description
TheDS90C032 is a quad CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion and high data rates. The device is designed to support
data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
TheDS90C032 accepts low voltage (350 mV) differential
input signals and translates them to CMOS (TTL compatible)
output levels. The receiver supports a TRI-STATE^® function
that may be used to multiplex outputs. The receiver also
supports OPEN, shorted and terminated (100Ω) input Fail-
safe with the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
TheDS90C032 and companion line driver (DS90C031) pro-
vide a new alternative to high power psuedo-ECL devices for
high speed point-to-point interface applications.
Features
n >155.5 Mbps (77.7 MHz) switching rates
n Accepts small swing (350 mV) differential signal levels
n Ultra low power dissipation
n 600 ps maximum differential skew (5V, 25˚C)
n 6.0 ns maximum propagation delay
n Industrial operating temperature range
n Military operating temperature range option
n Available in surface mount packaging (SOIC) and (LCC)
n Pin compatible with DS26C32A, MB570 (PECL) and
41LF (PECL)
n Supports OPEN, short and terminated input fail-safe
n Compatible with IEEE 1596.3 SCI LVDS standard
n Conforms to ANSI/TIA/EIA-644 LVDS standard
n Available to Standard Microcircuit Drawing (SMD)
5962-95834
Connection Diagrams
Dual-In-Line
LCC Package
01194501
Order Number
DS90C032TM
See NS Package Number M16A
01194520
Order Number
DS90C032E-QML
See NS Package Number E20A
For complete Military Specifications,
refer to appropriate SMD or MDS.
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS011945
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