DS8838 Datasheet, PDF (1/5 Pages) National Semiconductor (TI) – Quad Unified Bus Transceiver

May 1999
DS8838
Quad Unified Bus Transceiver
General Description
The DS8838 is a quad high speed driver/receiver designed
for use in bus organized data transmission systems intercon-
nected by terminated 120Ω impedance lines. The external
termination is intended to be 180Ω resistor from the bus to
the +5V logic supply together with a 390Ω resistor from the
bus to ground. The bus can be terminated at one or both
ends. Low bus pin current allows up to 27 driver/receiver
pairs to utilize a common bus. The bus loading is unchanged
when V_CC = 0V. The receivers incorporate hysteresis to
greatly enhance bus noise immunity. One two-input NOR
gate is included to disable all drivers in a package simulta-
neously. Receiver performance is optimized for systems with
bus rise and fall times ≤ 1.0 µs/V.
Features
n 4 totally separate driver/receiver pairs per package
n 1V typical receiver input hysteresis
n Receiver hysteresis independent of receiver output load
n Guaranteed minimum bus noise immunity of 1.3V, 2V
typ.
n Temperature-insensitive receiver thresholds track bus
logic levels
n 20 µA typical bus terminal current with normal V_CC or
with V_CC = 0V
n Open collector driver output allows wire-OR connection
n High speed
n Series 74 TTL compatible driver and disable inputs and
receiver outputs
Typical Application
DS005812-1
© 1999 National Semiconductor Corporation DS005812
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