CD4023M Datasheet, PDF (1/6 Pages) National Semiconductor (TI) – Triple 3-Input NAND(NOR) Gate

February 1988
CD4023M CD4023C Triple 3-Input NAND Gate
CD4025M CD4025C Triple 3-Input NOR Gate
General Description
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-chan-
nel enhancement mode transistors All inputs are protected
against static discharge with diodes to V_DD and V_SS
Features
Y _{Wide supply voltage range}
Y _{High noise immunity}
Y _{5V – 10V parametric ratings}
Y _{Low power}
3 0V to 15V
0 45 V_DD (typ )
Connection Diagrams
CD4023M CD4023C
Dual-In-Line Packages
CD4025M CD4025C
Top View
TL F 5955 – 1
Order Number CD4023 or CD4025
Top View
TL F 5955 – 2
C1995 National Semiconductor Corporation TL F 5955
RRD-B30M105 Printed in U S A