ADC10030 Datasheet, PDF (1/17 Pages) National Semiconductor (TI) – 10-Bit, 30 MSPS, 125 mW A/D Converter with Internal Sample and Hold

January 2000
ADC10030
10-Bit, 30 MSPS, 125 mW A/D Converter with Internal
Sample and Hold
General Description
The ADC10030 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 10 bits
resolution at sampling rates up to 30 Msps while consuming
a typical 125 mW from a single 5V supply. Reference force
and sense pins allow the user to connect an external refer-
ence buffer amplifier to ensure optimal accuracy. No missing
codes is guaranteed over the full operating temperature
range. The unique two-stage architecture achieves 9.1 Ef-
fective Bits with a 15 MHz input signal and a 30 MHz clock
frequency. Output formatting is straight binary coding.
To ease interfacing to 3V systems, the digital I/O power pins
of the ADC10030 can be tied to a 3V power source, making
the outputs 3V compatible. When not converting, power con-
sumption can be reduced by pulling the PD (Power Down)
pin high, placing the converter into a low power standby
state, where it typically consumes less than 4 mW. The
ADC10030’s speed, resolution and single supply operation
makes it well suited for a variety of applications in video, im-
aging, communications, multimedia and high speed data ac-
quisition. Low power, single supply operation ideally suit the
ADC10030 for high speed portable applications, and its
speed and resolution are ideal for charge coupled device
(CCD) input systems.
The ADC10030 comes in a space saving 32-pin TQFP and
operates over the industrial (−40˚C ≤ T_A ≤ +85˚C) tempera-
ture range.
Features
n Internal Sample-and-Hold
n Single +5V Operation
n Low Power Standby Mode
n Guaranteed No Missing Codes
n TRI-STATE^® Outputs
n TTL/CMOS or 3V Logic Input/Output Compatible
Key Specifications
n Resolution
n Conversion Rate
n ENOB @ 15 MHz Input
n DNL
n Conversion Latency
n PSRR
n Power Consumption
n Low Power Standby Mode
10 Bits
30 Msps
9.1 Bits (typ)
0.40 LSB (typ)
2 Clock Cycles
56 dB
125 mW (typ)
<3.5 mW (typ)
Applications
n Digital Video
n Communications
n Document Scanners
n Medical Imaging
n Electro-Optics
n Plain Paper Copiers
n CCD Imaging
Connection Diagram
TRI-STATE^® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS101064
DS101064-1
www.national.com